Zero voltage switching flyback converter

Patent metadata

Field	Value
Publication number	US-9843265-B2
Application number	US-201514973456-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Dec 17, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A zero voltage switching method for a flyback converter featuring a transformer with first and second primary windings and corresponding turns ratios, N1 and N2, includes rectifying and filtering an AC signal to produce a primary DC voltage. A voltage level signal indicating whether the primary DC voltage falls within a particular voltage range is generated. The voltage level signal is used to select a particular primary winding from either the first primary winding or the second primary winding. A PWM controller corresponding to the particular primary winding is activated and an output of the particular PWM controller performs zero voltage switching of a gate terminal of the applicable main switching transistor. A duty cycle of the main switching transistor is maintained within a range of approximately 50% to approximately 60% in accordance with the turns ratio and the primary DC voltage to achieve a desired output voltage.

First claim

What is claimed is:

1. A flyback converter comprising:
a rectifier configured to rectify an AC supply signal received from an AC power source to generate a rectified signal;
a bulk capacitor configured to filter the rectified signal to provide a primary DC voltage at a primary DC node;
a transformer including:
a first primary winding, comprising a first number of turns, coupled to the primary DC node;
a second primary winding, comprising a second number of turns, coupled to the primary DC node; and
a secondary winding;

a first main switching transistor including output terminals coupled in series with the first primary winding;
a second main switching transistor including output terminals coupled in series with the second primary winding;
a PWM circuit configured to:
provide a first output control signal to a control terminal of the first main switching transistor; and
provide a second output control signal to a control terminal of the second main switching transistor;

a voltage comparator configured to generate a voltage level indicator signal in accordance with a voltage of the primary DC voltage; and
a selection switch configured to enable one of the output control signals in accordance with the voltage level indicator signal;
a first peak limiting circuit coupled across the first primary winding; and
a second peak limiting circuit coupled across the second primary winding.

2. The flyback converter of claim 1 , wherein the rectifier comprises a bridge diode rectifier.

3. The flyback converter of claim 1 , wherein the first peak limiting circuit includes a Zener diode in series with a standard diode of opposing polarity.

4. The flyback converter of claim 1 , wherein the first peak limiting circuit permits reverse breakdown current to flow towards the primary DC node.

5. The flyback converter of claim 1 , wherein the voltage comparator includes a Schmitt trigger including a first input coupled to the primary DC node and a second comparator input coupled to a reference voltage.

6. A flyback converter comprising:
a rectifier configured to rectify an AC supply signal received from an AC power source to generate a rectified signal;
a bulk capacitor configured to filter the rectified signal to provide a primary DC voltage at a primary DC node;
a transformer including:
a first primary winding, comprising a first number of turns, coupled to the primary DC node;
a second primary winding, comprising a second number of turns, coupled to the primary DC node; and
a secondary winding;

a first main switching transistor including output terminals coupled in series with the first primary winding;
a second main switching transistor including output terminals coupled in series with the second primary winding;
a PWM circuit configured to:
provide a first output control signal to a control terminal of the first main switching transistor; and
provide a second output control signal to a control terminal of the second main switching transistor;

a voltage comparator configured to generate a voltage level indicator signal in accordance with a voltage of the primary DC voltage; and
a selection switch configured to enable one of the output control signals in accordance with the voltage level indicator signal;
wherein the PWM circuit includes a first PWM controller for the first main switching transistor and a second PWM controller for the second main switching transistor.

7. The flyback converter of claim 6 , wherein the selection switch couples a power supply signal to either the first PWM controller or the second PWM controller.

8. The flyback converter of claim 7 , wherein the voltage level indicator signal indicates whether the primary DC voltage is in a high voltage range or in a low voltage range.

9. The flyback converter of claim 8 , wherein N1 is greater than N2 and wherein the selection switch switches the power supply signal to the first PWM controller when the voltage level indicator signal indicates the primary DC voltage is in the high voltage range.

10. The flyback converter of claim 1 , further comprising a sense resistor connected between ground and a source node to which a source terminal of the first main switching transistor and a source terminal of the second main switching transistor are coupled.

11. An information handling system, comprising:
a processor;
a memory device coupled to the processor;
an internal DC-to-DC converter configured to receive a DC input voltage from a voltage converter; and
a flyback converter configured to provide the DC input voltage to the internal DC-to-DC converter, wherein the flyback converter includes:
rectifying circuitry configured to:
generate a primary DC voltage from an AC supply signal; and
provide the primary DC voltage to a primary DC node;

a transformer including:
a first primary winding, comprising a first number of turns, coupled to the primary DC node; and
a second primary winding, comprising a second number of turns, coupled to the primary DC node;

a first main switching transistor including output terminals coupled in series with the first primary winding;
a second main switching transistor including output terminals coupled in series with the second primary winding;
a PWM circuit configured to provide an output control signal to a control terminal of a particular main switching transistor, selected from the first main switching transistor and the second main switching transistor, to control a duty cycle of the particular main switching transistor in accordance with the primary DC voltage and the DC input voltage;
a voltage comparator configured to generate a voltage level indicator signal in accordance with the primary DC voltage; and
a selection switch configured to select the particular main switching transistor in accordance with the voltage level indicator signal;
wherein the PWM circuit includes a first PWM controller corresponding to the first main switching transistor and a second PWM controller corresponding to the second main switching transistor.

12. The information handling system of claim 11 , wherein the rectifying circuitry includes:
a diode bridge rectifier configured to receive the AC supply signal and generate a rectified signal; and
a bulk capacitor configured to filter the rectified signal to provide the primary DC voltage at the primary DC node.

13. The information handling system of claim 11 , wherein the voltage comparator includes a Schmitt trigger including a first input coupled to the primary DC node and a second input coupled to a reference voltage.

14. The information handling system of claim 11 , wherein the selection switch couples a power supply signal to either the first PWM controller or the second PWM controller.

15. The information handling system of claim 11 , wherein:
the first number of turns is greater than the second number of turns;
the voltage level indicator signal indicates whether the primary DC voltage is in a high voltage range or in a low voltage range; and
the selection switch selects:
the first main switching transistor as the particular switching transistor in accordance with the voltage level indicator indicating the primary DC voltage is in the high voltage range; and
the second main switching transistor as the particular switching transistor in accordance with the voltage level indicator indicating the primary DC voltage is in the low voltage range.

16. The information handling system of claim 11 , further comprising a sense resistor connected between ground and a source node to which a source terminal of the first main

Assignees

• Dell Products Lp

Inventors

• Yu wei cheng
• Liao Tsung-Cheng
• Chang Wen-Yung
• Wood Iii Merle Jackson
• Liang Tun-Chieh

Classifications

• H02M2001/0022

  Electricity · mapped topic

• H02M3/33569 Primary

  having several active switching elements (H02M3/3353 takes precedence) · CPC title

• H02M1/0022

  the disturbance parameters being input voltage fluctuations · CPC title