ESD protection circuit

Patent metadata

Field	Value
Publication number	US-9843183-B2
Application number	US-201514977012-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Apr 17, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An ESD protection circuit is disclosed, in which an RC trigger circuit and a transmission gate are used for determination of ESD protection triggering, and a silicon-controlled rectifier for ESD current conductance. The RC trigger circuit and the transmission gate allow improved trigger efficiency. In addition, the silicon-controlled rectifier incorporates first and second resistors, which can be implemented to have very low resistance values and are therefore able to effectively prevent the occurrence of latch-up during normal operation, as well as pull-up and pull-down transistors which can make an additional contribution to latch-up inhibition when turned on.

First claim

What is claimed is:

1. An ESD protection circuit, comprising: a trigger circuit, a plurality of inverters, a transmission gate, a first transistor, a second transistor, a first resistor, a second resistor, a pull-up transistor and a pull-down transistor, wherein: the plurality of inverters are connected in series and include a leading inverter and a trailing inverter; the transmission gate comprises an nMOS transistor and a pMOS transistor connected in parallel; the leading inverter has an input coupled to the trigger circuit; the trailing inverter has an output coupled to both a gate of the nMOS transistor of the transmission gate and a gate of the pull-up transistor; the trailing inverter has an input coupled to both a gate of the pMOS transistor of the transmission gate and a gate of the pull-down transistor; the first transistor has a base shorted with a collector of the second transistor; the second transistor has a base shorted with a collector of the first transistor; the second transistor has a collector coupled to an emitter of the first transistor via the first resistor, and the emitter of the first transistor is coupled to a power supply voltage; the first transistor has a collector coupled to an emitter of the second transistor via the second resistor, and the emitter of the second transistor is grounded; and the transmission gate has a first control terminal coupled to both a drain of the pull-up transistor and the base of the first transistor and has a second control terminal coupled to both a drain of the pull-down transistor and the base of the second transistor.

2. The ESD protection circuit according to claim 1 , wherein the plurality of inverters comprise three series-connected inverters.

3. The ESD protection circuit according to claim 1 , wherein the trigger circuit is a circuit consisting of a resistor and a capacitor connected in series, and the input of the leading inverter is coupled between the resistor and the capacitor.

4. The ESD protection circuit according to claim 3 , wherein the trigger circuit has a resistance-capacitance product ranging from 0 μS to 2 μS.

5. The ESD protection circuit according to claim 1 , wherein the pull-up transistor is pMOS transistor and the pull-down transistor is an nMOS transistor.

6. The ESD protection circuit according to claim 5 , wherein in normal operation, the transmission gate is turned off, and both of the pull-up transistor and the pull-down transistor are turned on.

7. The ESD protection circuit according to claim 1 , wherein in event of the trigger circuit being activated by an ESD current, the transmission gate is turned on, and upon a voltage difference between the base and the emitter of the first transistor exceeding a threshold voltage of the first transistor and a voltage difference between the base and the emitter of the second transistor exceeding a threshold voltage of the second transistor, the first transistor and the second transistor are turned on and form a positive feedback loop to discharge the ESD current, concurrently with the pull-up transistor and the pull-down transistor being turned off.

8. The ESD protection circuit according to claim 7 , wherein the voltage difference between the base and the emitter of the first transistor and the voltage difference between the base and the emitter of the second transistor are determined by a resistance ratio between the first resistor and the second resistor.

Assignees

• Shanghai Huahong Grace Semiconductor Mfg Corp

Inventors

• Lv Bin

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title