III-nitride transistor including a p-type depleting layer

Patent metadata

Field	Value
Publication number	US-9842922-B2
Application number	US-201615227240-A
Country	US
Kind code	B2
Filing date	Aug 3, 2016
Priority date	Jul 19, 2013
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

First claim

What is claimed is:

1. A transistor, comprising:
a III-N layer structure comprising a III-N buffer layer, a III-N depleting layer over the III-N buffer layer, a III-N channel layer over the III-N depleting layer, and a III-N barrier layer over the III-N channel layer, wherein the III-N channel layer includes a 2DEG channel therein;
a source and a drain; and
a gate between the source and the drain; wherein
the source electrically contacts the III-N depleting layer, and the drain is electrically isolated from the III-N depleting layer; and
the III-N channel layer extends continuously from the source to the drain.

2. The transistor of claim 1 , wherein the III-N depleting layer is a p-type layer.

3. A transistor, comprising:
a III-N layer structure comprising a III-N buffer layer, a III-N depleting layer over the III-N buffer layer, a III-N channel layer over the III-N depleting layer, and a III-N barrier layer over the III-N channel layer, wherein the III-N channel layer includes a 2DEG channel therein;
a source and a drain; and
a gate between the source and the drain; wherein
the source electrically contacts the III-N depleting layer, and the drain is electrically isolated from the III-N depleting layer;
the III-N depleting layer is a p-type III-N layer; and
a dopant concentration in the p-type III-N layer is such that an areal mobile charge density or a p-type doping density in the p-type III-N layer is in the range of 50-75% of an areal sheet charge density of mobile charge in the 2DEG channel.

4. The transistor of claim 3 , having a threshold voltage, wherein
mobile charge in the 2DEG channel between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased below the minimum voltage relative to the source, and
the minimum voltage is in a range of 20V to 100V.

5. A transistor, comprising:
a III-N layer structure comprising a III-N buffer layer, a III-N depleting layer over the III-N buffer layer, a III-N channel layer over the III-N depleting layer, and a III-N barrier layer over the III-N channel layer, wherein the III-N channel layer includes a 2DEG channel therein;
a source and a drain; and
a gate between the source and the drain; wherein
the source electrically contacts the III-N depleting layer, and the drain is electrically isolated from the III-N depleting layer;
the III-N depleting layer is a p-type III-N layer; and
the p-type III-N layer includes a superlattice comprising alternating p-doped III-N layers and un-doped III-N layers.

6. A transistor, comprising:
a III-N layer structure comprising a III-N buffer layer, a III-N depleting layer over the III-N buffer layer, a III-N channel layer over the III-N depleting layer, and a III-N barrier layer over the III-N channel layer, wherein the III-N channel layer includes a 2DEG channel therein;
a source and a drain; and
a gate between the source and the drain; wherein
the source electrically contacts the III-N depleting layer, and the drain is electrically isolated from the III-N depleting layer; and
the III-N depleting layer includes a superlattice comprising alternating III-N layers of varying bandgap or composition.

7. The transistor of claim 6 , where in the alternating III-N layers comprise alternating layers of GaN and AlGaN.

8. The transistor of claim 1 , wherein a portion of the III-N channel layer is below the drain and is between the drain and the III-N depleting layer.

9. The transistor of claim 1 , wherein the transistor further comprises a recess extending partially through the III-N barrier layer, and the gate is formed in the recess.

10. The transistor of claim 9 , wherein the transistor further comprises an insulating layer, the insulating layer being between the gate and the III-N barrier layer.

11. The transistor of claim 1 , wherein the transistor is an enhancement mode transistor.

12. A transistor, comprising:
a III-N layer structure comprising a III-N buffer layer, a III-N depleting layer over the III-N buffer layer, a III-N channel layer over the III-N depleting layer, and a III-N barrier layer over the III-N channel layer, wherein the III-N channel layer includes a 2DEG channel therein;
a source and a drain; and
a gate between the source and the drain; wherein
the 2DEG channel extends continuously from the source to the drain when the gate is biased relative to the source at a voltage which is higher than a threshold voltage of the transistor, and
the source electrically contacts the III-N depleting layer and the drain is electrically isolated from the III-N depleting layer.

13. The transistor of claim 12 , wherein the III-N depleting layer is a p-type layer.

14. The transistor of claim 13 , wherein a dopant concentration in the p-type III-N layer is such that an areal mobile charge density or a p-type doping density in the p-type III-N layer is in the range of 50-75% of an areal sheet charge density of mobile charge in the 2DEG channel.

15. The transistor of claim 14 , having a threshold voltage, wherein
mobile charge in the 2DEG channel between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased below the minimum voltage relative to the source, and
the minimum voltage is in a range of 20V to 100V.

16. The transistor of claim 13 , wherein the p-type III-N layer includes a superlattice comprising alternating p-doped III-N layers and un-doped III-N layers.

17. The transistor of claim 12 , wherein the III-N depleting layer includes a superlattice comprising alternating III-N layers of varying bandgap or composition.

18. The transistor of claim 17 , where in the alternating III-N layers comprise alternating layers of GaN and AlGaN.

19. The transistor of claim 12 , wherein a portion of the III-N channel layer is below the drain and is between the drain and the III-N depleting layer.

20. The transistor of claim 12 , wherein the transistor is an enhancement mode transistor.

Assignees

• Transphorm Inc

Inventors

• Mishra Umesh
• Lal Rakesh K
• Keller Stacia
• Chowdhury Srabanti

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/7783 Primary

  Electricity · mapped topic

• H01L29/51

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic