Array substrate and method of manufacturing the same, and display panel

Patent metadata

Field	Value
Publication number	US-9842867-B2
Application number	US-201615140723-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Sep 24, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

The present disclosure provides an array substrate and a method of manufacturing the same, and a display panel comprising the array substrate, for reducing a drop or height difference between surfaces of portions of a passivation layer located on either side of a source/drain electrode lead wire and a surface of a portion of passivation layer located on an upper surface of the source/drain electrode lead wire so as to increase an aperture ratio of the display panel. The method comprises: forming a source/drain electrode lead wire and a passivation layer successively on a base substrate, the passivation layer at least covering the source/drain electrode lead wire; and thinning a portion of the passivation layer located on the source/drain electrode lead wire such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, the method comprising steps of:
forming a source/drain electrode lead wire and a passivation layer in turn on a base substrate, the passivation layer covering at least the source/drain electrode lead wire; and
thinning a portion of the passivation layer located on a side of the source/drain electrode lead wire facing away from the base substrate such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein.

2. The method according to claim 1 , wherein the step of thinning the portion of the passivation layer located on the source/drain electrode lead wire comprises:
forming a photoresist layer on the passivation layer;
exposing and developing the photoresist layer with a mask so as to form a photoresist partially-remained region, a photoresist fully-removed region and a photoresist fully-remained region, the photoresist partially-remained region corresponding to the source/drain electrode lead wire and the photoresist fully-removed region corresponding to a region of the passivation layer where the via hole is to be formed;
thinning a portion of the passivation layer corresponding to the photoresist fully-removed region;
removing photoresist from the photoresist partially-remained region; and
thinning a portion of the passivation layer corresponding to the photoresist partially-remained region, while fully removing the portion of the passivation layer corresponding to the photoresist fully-removed region to form the via hole.

3. The method according to claim 2 , wherein thinning the portion of the passivation layer corresponding to the photoresist fully-removed region comprises:
etching the portion of the passivation layer corresponding to the photoresist fully-removed region.

4. The method according to claim 3 , wherein a thickness of the etched portion of the passivation layer corresponding to the photoresist fully-removed region is ¼˜⅓ of those of other portions of the passivation layer.

5. The method according to claim 2 , wherein thinning the portion of the passivation layer corresponding to the photoresist partially-remained region comprises:
etching the portion of the passivation layer corresponding to the photoresist partially-remained region.

6. The method according to claim 2 , further comprising:
stripping off the photoresist from the photoresist fully-remained region.

7. The method according to claim 2 , wherein the mask is a half tone mask, a gray tone mask or a mask having slits.

8. The method according to claim 1 , wherein a thickness of the thinned portion of the passivation layer located on the source/drain electrode lead wire is smaller than those of the other portions of the passivation layer.

9. The method according to claim 8 , wherein a thickness of the thinned portion of the passivation layer located on the source/drain electrode lead wire is ⅔˜¾ of those of the other portions of the passivation layer.

10. The method according to claim 2 , wherein a thickness of the thinned portion of the passivation layer located on the source/drain electrode lead wire is smaller than those of the other portions of the passivation layer.

11. The method according to claim 10 , wherein a thickness of the thinned portion of the passivation layer located on the source/drain electrode lead wire is ⅔˜¾ of those of the other portions of the passivation layer.

12. An array substrate manufactured by using the method of claim 1 , the array substrate comprising the source/drain electrode lead wire and the passivation layer formed in turn on the base substrate,
wherein the passivation layer covers at least the source/drain electrode lead wire, a surface of a portion of the passivation layer located on a side of the source/drain electrode lead wire facing away from the base substrate is higher than those of other portions of the passivation layer, and a thickness of the portion of the passivation layer located on the side of the source/drain electrode lead wire facing away from the base substrate is smaller than those of the other portions of the passivation layer.

13. The array substrate according to claim 12 , wherein the thickness of the thinned portion of the passivation layer located on the source/drain electrode lead wire is ⅔˜¾ of those of the other portions of the passivation layer.

14. An array substrate manufactured by using the method of claim 2 , the array substrate comprising the source/drain electrode lead wire and the passivation layer formed in turn on the base substrate,
wherein the passivation layer covers at least the source/drain electrode lead wire, a surface of a portion of the passivation layer located on the source/drain electrode lead wire is higher than those of other portions of the passivation layer, and a thickness of the portion of the passivation layer located on the source/drain electrode lead wire is smaller than those of the other portions of the passivation layer.

15. The array substrate according to claim 14 , wherein the thickness of the thinned portion of the passivation layer located on the source/drain electrode lead wire is ⅔˜¾ of those of the other portions of the passivation layer.

16. A display panel, comprising the array substrate according to claim 12 .

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Peng Junlin
• Yuan Shuai
• Huang Ming
• Zhao Lilu
• Xu Feng

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H01L27/1288 Primary

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic