Semiconductor packages with socket plug interconnection structures

Patent metadata

Field	Value
Publication number	US-9842822-B2
Application number	US-201514831463-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Apr 6, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first substrate;
socket bumps disposed on the first substrate and configured for providing insertion grooves;
a second substrate; and
plug bumps disposed on the second substrate, each of the plug bumps is configured for insertion into each of the insertion grooves, respectively, to electrically connect to the socket bumps, respectively,
wherein the socket bump includes a sidewall portion providing the inserting groove, and
wherein the plug bump is capable of moving up and down along an inner side surface of the sidewall portion of the socket bump in compliance with an external force.

2. The semiconductor package of claim 1 , wherein the first substrate comprises a semiconductor chip including integrated circuits.

3. The semiconductor package of claim 2 ,
wherein the second substrate comprises a package substrate, and
wherein the semiconductor chip is mounted on the package substrate.

4. The semiconductor package of claim 1 , wherein each of the socket bumps comprise sidewall pillars protruding from a first bottom portion of the socket bumps to substantially surround the insertion groove with the sidewall pillars.

5. The semiconductor package of claim 4 , wherein each of the sidewall pillars includes a line width less than a line width of the plug bump.

6. The semiconductor package of claim 1 ,
wherein each of the socket bumps comprises a sidewall protruding from first bottom portions of the socket bumps, respectively, and each of the sidewalls are configured to allow each of the plug bumps to remain within the insertion groves of the socket bumps, respectively.

7. A semiconductor package comprising:
a first substrate;
socket bumps disposed on the first substrate and configured for providing insertion grooves;
a second substrate;
plug bumps disposed on the second substrate, each of the plug bumps is configured for insertion into each of the insertion grooves, respectively, to electrically connect to the socket bumps, respectively; and
a retractile conductive connection member including a first end configured for being electrically connected on a bottom surface of the socket bump within the insertion groove and a second end connected to a front end of the inserted plug bump.

8. The semiconductor package of claim 7 ,
wherein the retractile conductive connection member comprises a conductive spring; and
wherein a first end of the conductive spring is combined with the surface of the socket bump within the insertion groove and an other end of the spring member is combined with the front end of the plug bump.

9. The semiconductor package of claim 8 , wherein the conductive spring comprises a spring coil.

10. The semiconductor package of claim 7 ,
wherein the retractile conductive connection member comprises conductive nano wires between the surface of the socket bump within the insertion groove and the front end of the plug bump, and
wherein the nano wires are bent or tangled with each other.

11. The semiconductor package of claim 7 , wherein the retractile conductive connection member comprises bent or tangled conductive carbon nanotubes between the surface of the socket bump within the insertion groove and the front end of the plug bump.

12. The semiconductor package of claim 7 , wherein the retractile conductive connection member comprises a conductive elastic member between the surface of the socket bump within the insertion groove and the front end of the plug bump.

13. The semiconductor package of claim 7 , wherein the retractile conductive connection member comprises a conductive polymer between the surface of the socket bump within the insertion groove and the front end of the plug bump.

14. The semiconductor package of claim 7 ,
wherein each of the socket bumps comprises a cylindrical sidewall portion protruding from a first bottom portion of the socket bump.

15. The semiconductor package of claim 14 ,
wherein the sidewall portion of the socket bump comprises at least two sidewalls separated from each other.

16. A semiconductor package comprising:
a first substrate;
socket bumps configured to protrude from a surface of the first substrate and provide insertion grooves within the socket bumps;
a second substrate positioned to face the first substrate;
plug bumps disposed to protrude from a surface of the second substrate toward the first substrate and configured for insertion into the insertion grooves of the socket bumps; and
a retractile conductive connection member including a first end configured for being electrically connected on a bottom surface of the socket bump within the insertion groove and a second end connected to a front end of the inserted plug bump,
wherein the plug bumps are configured to move in the insertion grooves with a reciprocating motion and are electrically connected to the socket bumps, respectively.

Assignees

• Sk Hynix Inc

Inventors

• Choi Hyeong Seok

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title