Integrated RF subsystem

Patent metadata

Field	Value
Publication number	US-9842814-B1
Application number	US-201615136835-A
Country	US
Kind code	B1
Filing date	Apr 22, 2016
Priority date	Apr 22, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

First claim

What is claimed is:

1. An integrated radio frequency (RF) subsystem comprising:
a chip substrate extending along a first direction;
a circuit patterned on a first surface of the chip substrate;
a probe electrically integrated with the circuit on a first side of the chip substrate, the probe and the circuit extending along the first direction; and
a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

2. The integrated RF subsystem of claim 1 , wherein the frame comprises:
a first side wall and a second side wall, the first and second side walls extending along the first direction;
a first cross wall and a second cross wall, the first and second cross walls laterally spaced from one another and extending along a second direction crossing the first direction, the first cross wall being spaced from an edge of the chip substrate; and
a base parallel to the chip substrate,
wherein the first cross wall, the first and second side walls, and the base define a second cavity at the edge of the chip substrate, and the first and second side walls and the first and second cross walls define the first cavity under the circuit.

3. The integrated RF subsystem of claim 2 ,
wherein the first cavity opens toward a third direction away from the substrate and crossing the first and second directions, and
wherein the second cavity opens toward the first direction.

4. The integrated RF subsystem of claim 2 , wherein the second cavity is configured to match a profile of, and be electromagnetically coupled to, a waveguide, the probe being positioned at a center of a cross-section of the waveguide orthogonal to the first direction.

5. The integrated RF subsystem of claim 2 , wherein a surface of the base facing the second side of the chip substrate is coated with an electrically conductive layer having a conductivity from about 30×10 6 Siemens/m to about 65×10 6 Siemens/m.

6. The integrated RF subsystem of claim 2 , wherein the first cross wall is aligned with an edge of the circuit coupled to the probe.

7. The integrated RF subsystem of claim 2 , wherein thicknesses of the first and second side walls and the base are substantially the same as those of corresponding walls of a waveguide coupled to the integrated RF subsystem.

8. The integrated RF subsystem of claim 1 , wherein the probe comprises an e-plane probe configured to receive an electromagnetic wave signal and to transmit an electrical signal to the circuit, the electrical signal corresponding to the electromagnetic wave signal.

9. The integrated RF subsystem of claim 1 , further comprising a heat spreader in the first cavity and configured to dissipate heat generated by the circuit.

10. The integrated RF subsystem of claim 9 , wherein the heat spreader contacts a second surface of the chip substrate.

11. The integrated RF subsystem of claim 9 , wherein the heat spreader comprises electroformed high thermal conductivity material comprising one or more of copper, copper alloys, silver, and gold.

12. The integrated RF subsystem of claim 1 , wherein an entire top surface of the frame is bonded to a second surface of the chip substrate.

13. The integrated RF subsystem of claim 1 , wherein the circuit comprises a monolithic microwave integrated circuit (MMIC).

14. The integrated RF subsystem of claim 1 , wherein the frame comprises one or more of Si, SiC, GaAs, GaN, InP, sapphire, and quartz.

15. A method of forming a wafer-level-fabricated RF subsystem, the method comprising:
receiving a mesh wafer having a plurality of first cavities arranged in matrix-form, and comprising a plurality of partition walls between the plurality of first cavities and extending along a first direction;
receiving an integrated circuit (IC) wafer comprising a plurality of circuits;
integrating a plurality of probes with the plurality of circuits on a first surface of the IC wafer;
aligning the mesh wafer with the IC wafer such that the plurality of partition walls of the mesh wafer are aligned to dicing streets between the plurality of circuits;
bonding the mesh wafer to a second surface of the IC wafer, the second surface facing oppositely from opposite the first surface; and
depositing a thermal heat spreader material in the plurality of first cavities to contact the second surface of the mesh wafer.

16. The method of claim 15 , wherein the first cavities are wafer-through openings and the second cavities are not wafer-through openings.

17. The method of claim 16 , wherein the plurality of second cavities are coated with an electrically conductive layer to form part of a waveguide, the electrically conductive layer having a conductivity from about 30×10 6 Siemens/m to about 65×10 6 Siemens/m.

18. The method of claim 15 , wherein the mesh wafer has a plurality of partial cavities arranged in matrix-form between the plurality of first cavities and the plurality of partition walls.

19. The method of claim 15 , wherein each of the plurality of first cavities corresponds in size to a respective circuit of the plurality of circuits.

20. The method of claim 15 , further comprising cutting the mesh wafer and the IC wafer along the dicing streets of the IC wafer to form a plurality of integrated RF subsystems, each of the plurality of integrated RF subsystems being integrated with a probe of the plurality of probes and a heat spreader of the thermal heat spreader material.

21. The method of claim 15 , further comprising performing planarization to level the thermal heat spreader material with a backside of the mesh wafer, the backside facing oppositely from opposite the second surface of the IC wafer.

22. The method of claim 15 , wherein the bonding further comprises attaching an entire top surface of the mesh wafer to a backside of the IC wafer.

23. The method of claim 15 , wherein the depositing of the thermal heat spreader material comprises electroforming a high thermal conductivity material comprising one or more of copper, copper alloys, silver, and gold as the thermal heat spreader material.

Assignees

• Hrl Lab Llc

Inventors

• Herrault Florian G
• Micovic Miroslav

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title