Method of producing a semiconductor package

Patent metadata

Field	Value
Publication number	US-9842792-B2
Application number	US-201615007607-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Aug 30, 2006
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

First claim

What is claimed is:

1. A semiconductor package comprising:
an electrically conductive layer having a plurality of holes at a top surface, wherein said plurality of holes are filled with a non-conductive material;
an electrically conductive foil on said top surface of said electrically conductive layer and said non-conductive material,
wherein said electrically conductive foil is in electrical communication with said electrically conductive layer;
wherein said electrically conductive foil is in direct physical contact with said non-conductive material that fills said plurality of holes;
wherein said conductive foil covers the entire top surface of said non-conductive material, in cross-section, that fills said plurality of holes; and
wherein said electrically conductive foil creates a network of leads, die pad, bus lines, dam bars and tie lines, wherein said bus lines connect said leads to said dam bar, said dam bar is connected to said tie line and said tie line is connected to said die pad; and

a semiconductor die attached to said die pad.

2. The semiconductor package of claim 1 further comprising:
a conductor material plating said leads and at least the periphery of said die pad;
a plurality of bond wires attached from said die to said leads;
an encapsulant covering said die and said plurality of wires; and
solder on the bottom of said leads.

3. The semiconductor package of claim 2 , wherein said conductor material is at least one of silver, gold, nickel, or copper.

4. The semiconductor package of claim 1 , wherein each of said plurality of holes extends from said top surface of said electrically conductive layer to a bottom surface of said electrically conductive layer.

5. The semiconductor package of claim 4 , further comprising a conductor material plating said bottom surface of said electrically conductive layer.

6. The semiconductor package of claim 5 , wherein said conductor material comprises solder balls.

7. The semiconductor package of claim 5 , wherein said conductor material comprises a conductive plating layer and a solder material layer.

8. The semiconductor package of claim 5 , wherein bottoms portions of said leads are electrically isolated from each other.

9. A semiconductor package comprising:
an electrically conductive layer having a plurality of holes at a top surface, wherein said plurality of holes are filled with a non-conductive material;
an electrically conductive foil on said top surface of said electrically conductive layer and said non-conductive material,
wherein said electrically conductive foil is in electrical communication with said electrically conductive layer;
wherein said electrically conductive foil is in direct physical contact with said non-conductive material that fills said plurality of holes;
wherein said conductive foil covers the entire top surface of said non-conductive material, in cross-section, that fills said plurality of holes; and
wherein said electrically conductive foil creates a network of leads, die pad, bus lines, dam bars and tie lines, wherein said bus lines connect said leads to said dam bar, said dam bar is connected to said tie line and said tie line is connected to said die pad; and

a solder mask attached to selected areas of said electrically conductive foil and said non-conductive material, wherein
said solder mask covers at least one inner row of leads, and
said solder mask has a plurality of openings that expose at least one outer row of leads and expose portions of said bus lines, that are connected to said inner row of leads, away from said inner row of leads;
a conductor material on selected areas of said top surface of said electrically conductive layer; and
a semiconductor die attached to portions of said conductor material and said solder mask.

10. The semiconductor package of claim 9 further comprising:
a conductor material plating said leads and at least the periphery of said die pad;
a plurality of bond wires attached from said die to said leads;
an encapsulant covering said die and said plurality of wires; and
solder on the bottom of said leads.

11. The semiconductor package of claim 10 , wherein said conductor material is at least one of silver, gold, nickel, or copper.

12. The semiconductor package of claim 9 , wherein each of said plurality of holes extends from said top surface of said electrically conductive layer to a bottom surface of said electrically conductive layer.

13. The semiconductor package of claim 12 , further comprising a conductor material plating said bottom surface of said electrically conductive layer.

14. The semiconductor package of claim 13 , wherein said conductor material comprises solder balls.

15. The semiconductor package of claim 13 , wherein said conductor material comprises a conductive plating layer and a solder material layer.

16. The semiconductor package of claim 13 , wherein bottoms portions of said leads are electrically isolated from each other.

17. The semiconductor package of claim 9 , wherein said semiconductor die overlaps said solder mask.

Assignees

• United Test And Assembly Center Ltd
• Utac Headquarters Pte Ltd

Inventors

• Retuta Danny
• Tan Hien Boon
• Sun Anthony Yi Sheng
• Cheong Mary Annie

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title