Non-volatile memory device for detecting progressive error, memory system, and method of operating the non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9842659-B2
Application number	US-201514616281-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Apr 7, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Provided are a non-volatile memory device, a memory system, and a method of operating the non-volatile memory device. The method includes: performing a user operation according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to a memory cell array; setting up voltages of a plurality of word lines; floating at least one word line from among the plurality of word lines, the voltages of which are set up, according to the at least one selected mode; and detecting whether the at least one word line has a progressive defect, according to a result of detecting a voltage level of the at least one floated word line.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a memory cell array connected to a plurality of word lines, and comprising a plurality of memory cells that are respectively connected to the plurality of word lines;
a voltage generator providing the memory cell array with word lines voltages, when a user operation is performed according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to the memory cell array; and
a voltage level detector detecting a voltage level of at least one word line that is floated according to the at least one selected mode, and generating a detection result representing whether the at least one word line has a progressive defect; and
a data determiner, wherein
the data determiner, if the writing mode is selected, is configured to determine a distribution of slow cells based on analyzing a distribution of threshold voltages of memory cells connected to the at least one word line, and at least one of,
the data determiner is configured to determine the at least one word line does not have the progressive defect if the slow cells are evenly distributed in the at least one word line, and
the data determiner is configured to determine the at least one word line has the progressive defect, if a number of the slow cells rapidly increases in a certain location of the at least one word line.

2. The non-volatile memory device of claim 1 , wherein the memory cell array comprises three-dimensional (3D) VNAND memory cells, and
the voltage generator, when the reading mode is selected, is configured to perform the reading mode to include a set up section for setting up the voltages and one or more sensing sections for sensing data, and a leakage monitoring section for detecting the progressive defect is inserted into the reading mode and performed after the set up section.

3. The non-volatile memory device of claim 1 , further comprising a data determiner,
wherein when the user operation of a first mode is selected, it is determined whether the at least one word line has the progressive defect, according to a result of detecting a voltage level of the at least one floated word line.

4. The non-volatile memory device of claim 1 , wherein
the plurality of memory cells in the memory call array are 3D VNAND memory cells,
the memory cell array includes a plurality of cell strings,
each of the cell strings includes a plurality of the 3D VNAND memory cells stacked on top of each other between a ground selection transistor and a string selection transistor, and
the 3D VNAND memory cells, ground selection transistor, and string selection transistor each include a charge trap flash structure.

5. A method of operating a non-volatile memory device, the method comprising:
entering a writing mode with respect to a memory cell array;
after performing predetermined writing loops, analyzing a distribution of threshold voltages of memory cells that are connected to one or more word lines;
determining a distribution of slow cells according to a result of the analyzing the distribution of the threshold voltages;
generating information representing whether the one or more word lines have a progressive defect, according to a result of the determining the distribution of the slow cells; and
determining whether the one or more word lines have the progressive defect based on the distribution of the slow cells, the determining whether the one or more word lines have the progressive defect including one of,
determining the one or more word lines do not have the progressive defect in response to the slow cells being evenly distributed in the one or more word lines, or
determining the one or more word lines have the progressive defect, if in response to a number of the slow cells rapidly increasing in a certain location of the one or more word lines.

6. The method of claim 5 , wherein when data of 2 bits or more is programmed in each of the memory cells in the memory cell array, the analyzing of the distribution of the threshold voltages includes performing the analyzing according to a result of identifying whether a current writing loop is a k-th writing loop, wherein k is an integer of 1 or greater.

7. The method of claim 5 , further comprising:
entering an erasing mode of the memory cell array;
detecting voltage levels of the one or more word lines; and
detecting the progressive defect in at least one word line among the one or more word lines, according to the detecting of the voltage levels of the one or more word lines.

8. The method of claim 5 , further comprising:
entering an erasing mode with respect to the memory cell array;
analyzing the distribution of threshold voltages of the memory cells that are connected to one or more word lines, when an erasing loop is performed; and
detecting the progressive defect according to a result of detecting a variation in a total number of memory cells in which verification failures have occurred in a same word line, or according to a result of comparing, among different word lines, a total number of memory cells in which verification failures have occurred.

9. The method of claim 5 , wherein
the memory cell array includes a plurality of cell strings,
each of the cell strings includes a plurality of 3D VNAND memory cells stacked on top of each other between a ground selection transistor and a string selection transistor, and
the 3D VNAND memory cells, ground selection transistor, and string selection transistor each include a charge trap flash structure.

10. The method of claim 5 ,
wherein a plurality of regions correspond to one word line,
wherein the determining the distribution of slow cells includes analyzing differences between bit error rates of the plurality of regions, and
determining whether the number of the slow cells rapidly increases is based on analyzing the differences.

Assignees

• Nam Sang-Wan
• Jeon Byung-Gil
• Byeon Dae-Seok
• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Jeon Byung-Gil
• Byeon Dae-Seok

Classifications

• G11C29/025 Primary

  in signal lines · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C2029/5006

  Current · CPC title