Nonvolatile memory device with improved reliability and operating speed

Patent metadata

Field	Value
Publication number	US-9842654-B2
Application number	US-201614996249-A
Country	US
Kind code	B2
Filing date	Jan 15, 2016
Priority date	Jul 6, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory blocks each including a plurality of cell strings, each cell string including a ground selection transistor, a plurality of memory cells, and a string selection transistor;
a row decoder circuit configured to apply a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device; and
a page buffer circuit configured to apply, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and to apply the first voltage and a second voltage lower than the first voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data, wherein
write data is loaded onto the page buffer circuit during the first precharge operation.

2. The nonvolatile memory device of claim 1 , wherein during the second precharge operation, the row decoder circuit applies the turn-on voltage to a string selection line selected from the string selection lines and applies a turn-off voltage to an unselected string selection line.

3. The nonvolatile memory device of claim 1 , wherein the first precharge circuit comprises a plurality of switches configured to supply, during the first precharge operation, a power supply voltage to the bit lines in response to a control signal.

4. The nonvolatile memory device of claim 1 , wherein the second precharge circuit comprises a plurality of switches configured to apply one of a power supply voltage and a ground voltage to each bit line in response to a value of each bit of data loaded onto the page buffer circuit, during the second precharge operation.

5. The nonvolatile memory device of claim 1 , wherein the page buffer circuit comprises:
latches corresponding to the bit lines and onto which the write data is loaded;
first transistors connected respectively between the bit lines and a power node and controlled in common by a control signal;
second transistors connected respectively between the bit lines and the power node and turned on or off according to values loaded onto the latches; and
third transistors connected respectively between the bit lines and a ground node and turned on or off according to values loaded onto the latches.

6. The nonvolatile memory device of claim 1 , wherein during a program operation, the row decoder circuit is configured to apply a program voltage to a selected word line and a pass voltage to unselected word lines from among word lines connected to memory cells of the selected memory block in response to the write command.

7. The nonvolatile memory device of claim 1 , wherein during a verification operation, the page buffer circuit applies a third voltage and a fourth voltage lower than the third voltage to the bit lines through the second precharge circuit, based on data loaded onto the page buffer circuit in response to the write command.

8. The nonvolatile memory device of claim 1 , wherein:
the first precharge operation, the second precharge operation, a program operation, and a verification operation which are performed according to the write command compose a program loop,
the program loop is performed iteratively, and
after at least one program loop is performed in response to the write command, the page buffer circuit is configured to apply the first voltage and the second voltage to the bit lines based on data loaded onto the page buffer circuit, during the second precharge operation.

9. The nonvolatile memory device of claim 1 , wherein:
in response to a read command received from the external device, the page buffer circuit is configured to apply a third voltage to the bit lines through the first precharge circuit at a first read precharge operation and to apply a first read voltage to a word line selected from word lines connected to memory cells of the selected memory block at a first read operation, and
in response to the read command, the page buffer circuit is configured to latch voltages on the bit lines at the first read operation.

10. The nonvolatile memory device of claim 9 , wherein in response to the read command, the page buffer circuit is further configured to apply the third voltage or a fourth voltage lower than the third voltage to the bit lines through the second precharge circuit at a second read precharge operation, based on the latched voltages.

11. A nonvolatile memory device comprising:
a memory cell array having memory cells that are each addressed by one of a plurality of bit lines and one of a plurality of word lines; and
a controller that executes a voltage application operation on the memory cells, wherein the controller:
a) applies, during a first pre-charge operation preceding the voltage application operation, a bit-line select signal to each of the bit lines, and
b) applies, during the execution of the voltage application operation, one of a plurality of word-line signals to each of the word lines, wherein
during a program operation, the controller further loads, within a data latch and during the first pre-charge operation, data values each of which corresponds to a respective one of the bit lines and indicates whether the bit line is to be selected or unselected for the voltage application operation.

12. The nonvolatile memory device of claim 11 , wherein, during the program operation, the controller further applies, during a second pre-charge operation preceding the voltage application operation, the bit-line select signal to each of the bits lines having a corresponding data value within the latch indicating that the bit line is to be selected for the voltage application operation and a bit-line unselect signal to each of the bits lines having a corresponding data value within the latch indicating that the bit line is to be unselected for the voltage application operation.

13. The nonvolatile memory device of claim 12 , wherein the controller read second data values from selected memory cells of the memory cell array in a read operation.

14. The nonvolatile memory device of claim 13 , wherein the controller applies, during a second pre-charge operation of the read operation, different voltages to the bit lines according to the second data values.

15. The nonvolatile memory device of claim 11 , wherein the controller executes operations (a) and (b) multiple times to program the data value into the memory cell.

Assignees

• Lee Ji-Sang
• Kwak Donghun
• Byeon Daeseok
• Yoon Chiweon
• Samsung Electronics Co Ltd

Inventors

• Lee Ji-Sang
• Kwak Donghun
• Byeon Daeseok
• Yoon Chiweon

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title