Method and system for designing semiconductor device

Patent metadata

Field	Value
Publication number	US-9842182-B2
Application number	US-201514845556-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Oct 1, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

First claim

What is claimed is:

1. A method of designing a semiconductor device, the method comprising:
providing a standard cell layout which comprises a plurality of active regions and a plurality of dummy regions, wherein at least one of the plurality of the dummy regions is interposed between the plurality of the active regions;
determining, using at least one microprocessor, a first fin pitch between a first active fin and a second active fin in at least one active region of the plurality of active regions and a second fin pitch between a first dummy fin and a second dummy fin in the at least one dummy region that is interposed between the plurality of active regions;
placing, using the at least one microprocessor the first and second active fins in the at least one active region and the first and second dummy fins in the at least one dummy region that is interposed between the plurality of active regions using the first and second fin pitches;
verifying, using the at least one microprocessor, the placement of the active fins and the dummy fins in the standard cell layout; and
updating the standard cell layout based on the verifying.

2. The method of claim 1 , wherein the first fin pitch and the second fin pitch are different.

3. The method of claim 1 , further comprising determining a third fin pitch between the second active fin and the first dummy fin.

4. The method of claim 3 , wherein the first through third fin pitches are different from one another.

5. The method of claim 1 , further comprising placing first through n-th metal lines in the standard cell layout, wherein the first through n-th metal lines are placed such that first through (n−1)-th metal pitches between adjacent metal lines are equal.

6. The method of claim 5 , wherein a cell height of the standard cell layout is CH, each of the first through (n−1)-th metal pitches is MetP, and CH=R×MetP, where R is a rational number.

7. The method of claim 6 , wherein a pitch between the second active fin and the first dummy fin is a fourth fin pitch, wherein the first fin pitch, the second fin pitch, and the fourth fin pitch are different from one another.

8. The method of claim 7 , further comprising placing a third dummy fin on at least one boundary line of the standard cell layout.

9. The method of claim 1 , further comprising defining the plurality of active regions and the at least one dummy region using a marker.

10. A method of designing a semiconductor device, the method comprising:
providing a standard cell layout which comprises a plurality of active regions and at least one dummy region;
determining, using at least one microprocessor, first and second fin pitches such that a plurality of active fins having the first fin pitch are placed in at least one active region of the plurality of active regions and that a plurality of dummy fins having the second fin pitch are placed in the dummy region;
determining, using the at least one microprocessor, a third fin pitch between an active fin of the plurality of active fins and a dummy fin of the plurality of dummy fins such that dummy fins are respectively placed on boundary lines of the standard cell layout which face each other in a direction of a cell height;
placing, using the at least one microprocessor, the active fins in the at least one active region and the dummy fins in the dummy region using the first through third fin pitches;
verifying, using the at least one microprocessor, the placement of the active fins and dummy fins in the standard cell layout; and
updating the standard cell layout based on the verifying.

11. The method of claim 10 , wherein the first through third fin pitches are different from one another.

12. The method of claim 10 , wherein in the placing the active fins in the at least one active region and the dummy fins in the dummy region, a first dummy fin and a second dummy fin are respectively placed on the boundary lines, the active fins are placed in the at least one active region, and the dummy fins are placed in the dummy region.

13. The method of claim 10 , further comprising placing a plurality of metal lines in the standard cell layout, wherein the metal lines are placed such that metal pitches between adjacent metal lines are equal.

14. The method of claim 13 , wherein the cell height is CH, each of the metal pitches is MetP, and CH=R×MetP, where R is a rational number.

15. A system for designing a semiconductor device, the system comprising:
a processor; and
a storage which stores an operation module executed using the processor,
wherein the operation module receives a standard cell layout which comprises a plurality of active regions and at least one dummy region, determines a first fin pitch between a first active fin and a second active fin in at least one active region of the plurality of active regions and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region, and places the first and second active fins in the at least one active region and the first and second dummy fins in the dummy region using the first and second fin pitches,
wherein the operation module further determines a third fin pitch between the second active fin and the first dummy fin,
wherein the operation module places a third dummy fin on at least one boundary line of the standard cell layout,
wherein the operation module verifies the placement of the active fins and dummy fins in the standard cell layout, and updates the standard cell layout based on the verification.

16. The system of claim 15 , wherein the first fin pitch and the second fin pitch are different.

17. The system of claim 15 , wherein the first through third fin pitches are different from one another.

18. The system of claim 15 , wherein the operation module further places first through n-th metal lines in the standard cell layout, wherein the first through n-th metal lines are placed such that first through (n−1)-th metal pitches between adjacent metal lines are equal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon
• Song Tae-Joong
• Yang Gi-Young
• Do Jeong-Ho

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2117/06

  Spare resources, e.g. for permanent fault suppression · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5072 Primary

  Physics · mapped topic

• H01L29/6681

  Electricity · mapped topic