Control server system with a switch and comparing circuit for controlling a trigger time for buffer and power signal based on current status

Patent metadata

Field	Value
Publication number	US-9842077-B2
Application number	US-201514808857-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Jun 9, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A control system includes a switch circuit, a buffering circuit, and a motherboard. The switch circuit is configured to output a switch signal having a trigger time. The buffering circuit determines whether the trigger time of the switch signal is equal to a predetermined time. If the trigger time of the switch signal is equal to the predetermined time, the buffering circuit outputs a signal to the motherboard. The motherboard performs a power off operation.

First claim

What is claimed is:

1. A control system, comprising:
a switch circuit configured to output a switch signal having a trigger time;
a first buffering circuit electrically coupled to the switch circuit, wherein the first buffering circuit receives the switch signal from the switch circuit, and outputs a first buffering signal according to the switch signal;
a second buffering circuit electrically coupled to the switch circuit, wherein the second buffering circuit determines whether the trigger time of the switch signal is equal to a predetermined time, the second buffering circuit outputs a second buffering signal with a first status in respond to the trigger time is equal to the predetermined time, the second buffering circuit outputs the second buffering signal with a second status when the trigger time of the switch signal is less than the predetermined time; and
a comparing circuit electrically coupled to the first and second buffering circuits, wherein the comparing circuit outputs a power signal with a first status, in event that the comparing circuit receives the first buffering signal and the second buffering signal with the first status.

2. The control system of claim 1 , wherein the comparing circuit outputs the power signal with the first status to a motherboard, and the motherboard performs a power off operation.

3. The control system of claim 1 , wherein the comparing circuit outputs the power signal with a second status in respond to receiving the first buffering signal and the second buffering signal with the second status.

4. The control system of claim 3 , wherein the first buffering circuit comprises a first buffering chip, the first buffering chip comprise an enable pin, an input pin, and an output pin, when the enable pin of the first buffering chip is at a low voltage level, the voltage level outputted by the output pin of the first buffering chip is the same as the voltage level of the input pin of the first buffering chip.

5. The control system of claim 4 , wherein the second buffering circuit comprises a second buffering chip, the second buffering chip comprise an enable pin, a input pin, and an output pin, when the enable pin of the second buffering chip is at a high voltage level, the voltage level outputted by the output pin of the second buffering chip is the same as the voltage level of the input pin of the second buffering chip.

6. The control system of claim 5 , wherein the comparing circuit comprise an OR gate, a first input pin of the OR gate electrically coupled to the first buffering circuit, to receive the first buffering signal; a second input pin of the OR gate electrically coupled to the second buffering circuit, to receive the second buffering signal; an output pin of the OR gate is configured to output the power signal.

7. The control system of claim 6 , wherein the switch circuit comprises a switch, a first terminal of the switch is electrically coupled to ground, a second terminal of the switch is configured to output the switch signal.

8. The control system of claim 7 , wherein the trigger time of the switch signal has relationship to the time that the switch being pushed.

9. The control system of claim 7 , wherein the first buffering circuit further comprise first to third resistors, the input pin of the first buffering pin is electrically coupled to the second terminal of the switch, a ground pin of the first buffering chip is electrically coupled to ground, a power pin of the first buffering chip is electrically coupled to a power terminal, the enable pin of the first buffering chip is electrically coupled to the power terminal through the first resistor, and electrically coupled to ground through the second resistor, the output pin of the first buffering chip is electrically coupled to the first input pin of the OR gate, and is electrically coupled to the power terminal through the third resistor.

10. The control system of claim 9 , wherein the second buffering circuit further comprises a delay chip, a capacitor, and fourth to eighth resistors; the input pin of the second buffering chip is electrically coupled to the second terminal of the switch through the fourth resistor, an power pin of the second buffering chip is electrically coupled to the power terminal, a ground pin of the second buffer chip is electrically coupled to ground, the enable pin of the second buffering chip is electrically coupled to a reset pin of the delay chip, the output pin of the second buffering chip is electrically coupled to the reset input pin of the delay chip, the output pin of the second buffering chip is further electrically coupled to the power terminal through the fifth resistor; a signal pin of the delay chip is electrically coupled to the power terminal, an delay pin of the delay chip is electrically coupled to ground through the capacitor, the power pin of the delay chip is electrically coupled to the power terminal, the reset pin of the delay chip is electrically coupled to the power terminal through the sixth resistor, the reset pin of the delay chip is electrically coupled to the second input pin of the OR gate, and electrically coupled to ground through the seventh resistor, the reset pin of the delay chip is electrically coupled to the power terminal through the eighth resistor.

11. The control system of claim 10 , wherein the output pin of the OR gate is electrically coupled to the power terminal through a ninth resistor.

12. A control system, comprising:
a switch configured to output a switch signal having a trigger time;
a first buffer circuit electrically coupled to the switch and configured to output a first buffering signal according to the switch signal;
a second buffer circuit electrically coupled to the switch circuit, the second buffering circuit being configured to (a) determine whether the trigger time of the switch signal is equal to a predetermined time, and (b) output a second buffering signal with a first status in response to the trigger time being equal to the predetermined time, the second buffering circuit outputs the second buffering signal with a second status when the trigger time of the switch signal is less than the predetermined time; and
a comparing circuit electrically coupled to the first and second buffering circuits configured to output a power signal with a first status in response to receiving the first buffering signal and the second buffering signal with the first status.

Assignees

• Hong Fu Jin Prec Industry (Shenzhen) Co Ltd
• Hon Hai Prec Ind Co Ltd
• Hong Fu Jin Prec Industry (Shezhen) Co Ltd

Inventors

• Gao Yang
• Wu Kang

Classifications

• G06F1/266

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• H01H13/50

  having a single operating member · CPC title

• G06F1/24

  Resetting means · CPC title