Methods of bus arbitration for low power memory access

Patent metadata

Field	Value
Publication number	US-9842068-B2
Application number	US-76024010-A
Country	US
Kind code	B2
Filing date	Apr 14, 2010
Priority date	Apr 14, 2010
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Systems and method for arbitrating requests to a shared memory system for reducing power consumption of memory accesses, comprises determining power modes associated with memory channels of the shared memory system, assigning priorities to the requests based at least in part on the power modes, and scheduling the requests based on the assigned priorities. Latency characteristics and page hit rate are also considered for assigning the priorities.

First claim

What is claimed is:

1. A method of arbitrating requests from bus masters for access to shared memory in a processing system comprising:
dividing the shared memory into memory channels;
determining power modes associated with the memory channels;
assigning priorities to the requests based at least in part on the power modes; and
scheduling the requests based on the assigned priorities.

2. The method according to claim 1 , wherein the power mode associated with a memory channel comprises a powered up mode and a powered down mode for the memory channel.

3. The method according to claim 2 , wherein assigning priorities to the requests based at least in part on the power modes comprises maximizing a duration of the powered down mode.

4. The method according to claim 1 , further comprising associating latency characteristics with the bus masters and assigning priorities to the requests based on latency characteristics of the bus masters.

5. The method of claim 1 , further comprising associating pages in the shared memory with the requests, and assigning priorities to the requests based on maximizing page hit rate.

6. The method of claim 1 , wherein the processing system further comprises:
a bus interconnect system to couple the bus masters to the memory channels;
memory controllers to control access to the memory channels and monitor the power modes of the memory channels;
a power mode register coupled to the memory channels, to store power mode information of the memory channels; and
bus arbiters coupled to the memory controllers and the power mode register, to assign priorities to the requests based at least in part on the power modes.

7. A processing system comprising:
a shared memory system divided into memory channels;
bus masters configured to generate requests to the shared memory system;
memory controllers configured to determine power modes associated with the memory channels; and
bus arbiters configured to assign priorities to the requests based at least in part on the power modes.

8. The processing system of claim 7 , wherein the power mode associated with a memory channel comprises a powered up mode and a powered down mode for the memory channel.

9. The processing system of claim 8 , wherein assigning priorities to the requests based at least in part on the power modes comprises maximizing a duration of the powered down mode.

10. The processing system of claim 7 , wherein assigning priorities to the requests based at least in part on the power modes further comprises associating latency characteristics with the bus masters and assigning priorities to the requests based on the latency characteristics of the bus masters.

11. The processing system of claim 7 , wherein assigning priorities to the requests based at least in part on the power modes further comprises associating pages in the shared memory with the requests, and assigning priorities to the requests based on maximizing page hit rate.

12. The processing system of claim 7 further comprising a power mode register coupled to the memory channels and bus arbiters, to store power mode information of the memory channels.

13. A processing system comprising:
a shared memory divided by memory channel means;
bus master means for sending requests to the shared memory system;
means for determining power modes associated with the memory channels;
means for assigning priorities to the requests based at least in part on the power modes; and
means for scheduling the requests based on the assigned priorities.

14. The processing system of claim 13 , wherein the power mode associated with a memory channel comprises a powered up mode and a powered down mode for the memory channel.

15. The processing system of claim 14 , wherein means for assigning priorities to the requests based at least in part on the power modes comprises means for maximizing a duration of the powered down mode.

16. The processing system of claim 13 , further comprising means for associating latency characteristics with the bus masters and means for assigning priorities to the requests based on latency characteristics of the bus masters.

17. The processing system of claim 13 , further comprising means for associating pages in the shared memory with the requests, and means for assigning priorities to the requests based on maximizing page hit rate.

18. A method of arbitrating requests from bus masters for access to shared memory in a processing system comprising:
step for dividing the shared memory into memory channels;
step for determining power modes associated with the memory channels;
step for assigning priorities to the requests based at least in part on the power modes; and
step for scheduling the requests based on the assigned priorities.

19. The method according to claim 18 , wherein the power mode associated with a memory channel comprises a powered up mode and a powered down mode for the memory channel.

20. The method according to claim 19 , wherein the step for assigning priorities to the requests based at least in part on the power modes comprises a step for maximizing a duration of the powered down mode.

21. The method according to claim 18 , further comprising a step for associating latency characteristics with the bus masters and a step for assigning priorities to the requests based on latency characteristics of the bus masters.

22. The method according to claim 18 , further comprising a step for associating pages in the shared memory with the requests, and a step for assigning priorities to the requests based on maximizing page hit rate.

23. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for arbitrating request from bus masters for access to a shared memory divided into memory channels, the non-transitory computer-readable storage medium comprising:
code for determining power modes associated with the memory channels;
code for assigning priorities to the requests based at least in part on the power modes; and
code for scheduling the requests based on the assigned priorities.

Assignees

• Wang Feng
• Qualcomm Inc

Inventors

• Wang Feng

Classifications

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F13/161 Primary

  with latency improvement · CPC title

• G06F13/1684

  using multiple buses · CPC title

• G06F1/32 Primary

  Means for saving power · CPC title

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title