Integrated circuit comprising an IO buffer driver and method therefor

Patent metadata

Field	Value
Publication number	US-9842066-B2
Application number	US-201214398876-A
Country	US
Kind code	B2
Filing date	May 31, 2012
Priority date	May 31, 2012
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

First claim

The invention claimed is:

1. An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising:
at least one input signal;
a primary buffer driver stage for receiving the at least one input signal and providing an output signal in a first time period; and
a secondary buffer driver stage for receiving the at least one input signal and providing an output signal in a second time period;
a processor module configured to monitor and identify when a bias temperature instability (BTI) degradation condition may be met, and in response thereto effect switching of the IO buffer driver circuit output from the primary buffer driver stage to the secondary buffer driver stage operation,
wherein the primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a variable output signal.

2. The integrated circuit of claim 1 wherein the first time period is different to the second time period.

3. The integrated circuit of claim 1 wherein the first time period overlaps the second time period.

4. The integrated circuit of claim 1 wherein the processor module is operably coupled to a timer circuit arranged to ensure that the first time period is different to the second time period.

5. The integrated circuit of claim 1 wherein the primary buffer driver stage is connected in parallel to the secondary buffer driver stage.

6. The integrated circuit of claim 1 wherein the secondary buffer driver stage is configured to maintain at an output of the IO buffer driver circuit a previous value generated by the primary driver stage.

7. The integrated circuit of claim 6 wherein the secondary buffer driver stage is configured to maintain the previous value generated by the primary driver stage, whilst the primary driver stage is switched off.

8. The integrated circuit of claim 1 wherein the secondary buffer driver stage is a size factor smaller than the primary buffer driver stage.

9. The integrated circuit of claim 1 wherein a latch element is operably coupled to the secondary buffer driver stage and arranged to receive the at least one input signal and provide a latched input signal to the secondary buffer driver stage.

10. The integrated circuit of claim 1 wherein the secondary buffer driver stage is switched off when in a steady state condition whilst the primary driver is switched on.

11. The integrated circuit of claim 1 wherein the secondary buffer driver stage is part of and cooperates with the primary driver stage.

12. The integrated circuit of claim 1 wherein the secondary buffer driver stage is switched off when in a steady state condition whilst the primary driver is switched on and the processor module is configured to apply an automatic switching of the IO buffer driver circuit output from the primary buffer driver stage to the secondary buffer driver stage operation.

13. The integrated circuit of claim 1 wherein the processor module is configured to adapt a toggling frequency of switching of the IO buffer driver circuit output from the primary buffer driver stage to the secondary buffer driver stage operation, dependent upon an IO buffer driver application and/or at least one prevailing operating condition.

14. A method for bias stress condition removal in a circuit comprising at least one input/output (IO) buffer driver circuit, the method comprising:
receiving at least one input signal at a primary buffer driver stage and providing an output signal in a first time period;
receiving the at least one input signal at a secondary buffer driver stage and providing an output signal in a second time period, wherein the primary buffer driver stage and the secondary buffer driver stage cooperate;
varying an operational mode of the primary buffer driver stage and varying an operational mode of the secondary buffer driver stage to produce a variable output signal; and
adapting a toggling frequency of switching of the IO buffer driver circuit output from the primary buffer driver stage to the secondary buffer driver stage operation, dependent upon an IO buffer driver application and/or at least one prevailing operating condition.

Assignees

• Priel Michael
• Kuzmin Dan
• Sofer Sergey
• Nxp Usa Inc

Inventors

• Priel Michael
• Kuzmin Dan
• Sofer Sergey

Classifications

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/1087

  Data input latches · CPC title