Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction

Patent metadata

Field	Value
Publication number	US-9842048-B2
Application number	US-201514939863-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Jul 30, 2009
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A method of block deinterleaving data received at a digital radio broadcast receiver is described. The method includes providing a block of memory having a n×k addresses, wherein the block comprises a single table, receiving a digital radio broadcast signal at the receiver, and demodulating the digital radio broadcast signal into a plurality of interleaved data units. For at least one series of n×k data units a pointer step size is determined, and for each data unit in the series, an address in the block is calculated based on the pointer step size, and an output data unit is read from the block at the address, such that said output data units represent block deinterleaved data units. An input data unit from the plurality of interleaved data units is then written to the block at the address. Associated systems and computer readable storage media are presented.

First claim

What is claimed is:

1. A processor-implemented method of block deinterleaving data received at a digital radio broadcast receiver comprising:
a. providing a block of memory having n×k addresses, wherein the block comprises a single table, and each of n and k is a non-zero, positive integer;
b. receiving a digital radio broadcast signal at the digital radio broadcast receiver;
c. demodulating the digital radio broadcast signal into a plurality of interleaved data units;
d. for a current series of n×k interleaved data units,
i. calculating a pointer step size according to size of the current series of interleaved data units and a pointer step size of a previous series of interleaved data units; and
ii. for each interleaved data unit in the current series,
1. calculating an address in the block based on the pointer step size;
2. reading an output data unit from the block at the calculated address, such that said output data units represent block deinterleaved data units; and
3. writing an input data unit from the plurality of interleaved data units to the block at the same calculated address prior to reading and writing a subsequent output data unit.

2. The processor-implemented method of claim 1 wherein said input data units are not sequentially ordered in the block of memory.

3. The processor-implemented method of claim 1 wherein the pointer step size Psz is determined as follows:
P temp =MOD( Psz (m-1) ·k ,( n·k ))+└ Psz (m-1) /( n )┘; and  a.

Psz (m) =MOD( P temp ,( n·k ))+└ P temp /( n·k )┘,  b.

where m is an index corresponding to a given set of n×k data units and P temp is a temporary step size variable.

4. The processor-implemented method of claim 3 , wherein for a first iteration of deinterleaving, the pointer step size is set to Psz (1) =1.

5. The processor-implemented method of claim 3 wherein each address in the block is calculated as follows:
a. For i from 1 to n×k, the address (ADDRp) is as follows,
for i= 1,ADDR p (1)=1;  i.

for iε [2,( n·k− 1)],ADDR p ( i )=MOD((ADDR p ( i− 1)+ Psz ),( n·k ))±└(ADDR p ( i− 1)± Psz )/( n·k )┘;  ii.

for i=n·k ,ADDR p ( n·k )= n·k.   iii.

6. The processor-implemented method of claim 1 wherein the interleaved data units are bits.

7. The processor-implemented method of claim 1 comprising:
reading the output data units from the block for a first series and writing the input data units to the block for a next series interleaved of data units, such that writing some of the input data units to the block for the next series is performed before reading the output data units from the block for the first series is completed,
wherein reading and writing from and to the block are done from and to non-sequential addresses.

8. The processor-implemented method of claim 1 , wherein
the reading of the output data unit comprises a read operation,
the writing of the input data unit comprises a write operation performed after the read operation, and
the read operation and the mite operation are consecutive operations.

9. The processor-implemented method of claim 8 , wherein the read operation and the write operation are performed using a single address pointer.

10. A digital radio broadcast receiver configured to perform block deinterleaving of data comprising:
a processing system; and
a memory coupled to the processing system, wherein the processing system is configured to execute steps comprising:
a. providing a block of memory having n×k addresses, wherein the block comprises a single table, and each of n and k is a non-zero, positive integer;
b. receiving a digital radio broadcast signal at the digital radio broadcast receiver;
c. demodulating the digital radio broadcast signal into a plurality of interleaved data units;
d. for a series of n×k interleaved data units,
i. calculating a pointer step size according to size of the series of interleaved data units and a pointer step size of a previous series of interleaved data units; and
ii. for each interleaved data unit,
1. calculating an address in the block based on the pointer step size;
2. reading an output data unit from a first series of data units from the block at the address, such that said output data units represent block deinterleaved data units; and
3. writing an input data unit from a second series of interleaved data units to the block at the same address prior to reading and writing another output data unit.

11. The digital radio broadcast receiver of claim 10 wherein said input data units are not sequentially ordered in the block of memory.

12. The digital radio broadcast receiver of claim 10 wherein the pointer step size Psz is determined as follows:
P temp =MOD( Psz (m-1) ·k ,( n·k ))+└ Psz (m-1) /( n )┘; and  a.

Psz (m) =MOD( P temp ,( n·k ))+└ P temp /( n·k )┘,  b.

where in is an index corresponding to a given set of n×k interleaved data units and P temp is a temporary step size variable.

13. The digital radio broadcast receiver of claim 12 , wherein for a first iteration of deinterleaving, the pointer step size is set to Psz (1) =1.

14. The digital radio broadcast receiver of claim 12 wherein each address in the block is calculated as follows:
a. For i from 1 to n×k, the address (ADDRp) is as follows,
for i= 1,ADDR p (1)=1;  i.

for iε [2,( n·k− 1)],ADDR p ( i )=MOD((ADDR p ( i− 1)+ Psz ),( n·k ))+└(ADDR p ( i− 1)+ Psz )/( n·k )┘,  ii.

for i=n·k ,ADDR p ( n·k )= n·k   iii.

15. The digital radio broadcast receiver of claim 10 wherein the interleaved data units are bits.

16. The digital radio broadcast receiver of claim 10 comprising:
reading the output data units from the block for a first series and writing the input data units to the block for a next series of interleaved data units, such that writing some of the input data units to the block for the next series is performed before reading the output data units from the block for the first series is completed,
wherein reading and writing from and to the block are done from and to non-sequential addresses.

17. The digital radio broadcast receiver of claim 10 , wherein the reading of the output data unit comprises a read operation,
the writing of the input data unit comprises a write operation performed after the read operation, and
the read operation and the write operation are consecutive operations.

18. The digital radio broadcast receiver of claim 17 , wherein the read operation and the write operation are performed using a single address pointer.

19. An article of manufacture comprising a non-transitory computer readable storage medium having computer program instructions adapted to cause a processing system to execute steps comprising:
a. providing a block of memory having n×k addresses, wherein the block comprises a single table, and each of n and k is a non-zero, positive integer;
b. receiving a digital radio broadcast signal at the digital radio broadcast receiver;
c. demodulating the digital radio broadcast signal into a plurality of interleaved data units;
d. for a current series of n×k interleaved data units,
i. calculating a pointer step size according to size of the current series of interleaved data units and a pointer step size of a previous series of interleaved data units; and
ii. for each interleaved data unit in the series,
1. calculating an address in the block based on the pointer step size;
2. reading an output data unit from the block at the calculated address, such that said output data units represent

Assignees

• Ibiquity Digital Corp

Inventors

• Milbar Marek

Classifications

• H03M13/2785

  Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location · CPC title

• H04W52/0206

  in access points, e.g. base stations · CPC title

• H04H2201/18

  in band on channel [IBOC] · CPC title

• G06F2212/174

  Telecommunications system · CPC title

• H03M13/6569

  Implementation on processors, e.g. DSPs, or software implementations · CPC title