Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines

Patent metadata

Field	Value
Publication number	US-9842005-B2
Application number	US-201213428438-A
Country	US
Kind code	B2
Filing date	Mar 23, 2012
Priority date	Mar 25, 2011
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

First claim

What is claimed is:

1. A system for executing instructions using a plurality of register file segments for a processor, comprising:
a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions;
a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein resources of each partitionable engine are operable to be partitioned to instantiate a virtual core with partitioned resources of other partitionable engines, wherein communication between resources of each of said plurality of partitionable engines is supported by a global interconnection structure, and wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode; and
a plurality of register file segments coupled to the partitionable engines for providing data storage, wherein the global interconnection structure links each of the plurality of register file segments to each of the plurality of partitionable engines.

2. The system of claim 1 wherein the plurality of register file segments implement an execution mode wherein a subset of physical resources of each register file segment are allocated to support execution of a single logical thread of a logical core.

3. The system of claim 2 , wherein each register file segment implements a portion of a plurality of logical cores.

4. The system of claim 1 , wherein the plurality of register file segments implement an execution mode wherein physical resources of each register file segment are dynamically allocated in accordance with an adjustable threshold to support execution of a single logical thread of a single logical core.

5. The system of claim 4 , wherein the plurality of register file segments implement a portion of a plurality of logical cores.

6. The system of claim 1 , wherein the plurality of register file segments implement an execution mode wherein the set of physical resources of each register file segment are allocated to support execution of a single logical thread.

7. The system of claim 1 , wherein each register file segment further comprises a common partition scheduler, an operand and result buffer and a threaded register file.

8. The system of claim 1 , wherein the global interconnection structure comprises a routing matrix operable to allow the plurality of partitionable engines to access data stored at any point in the plurality of register file segments.

9. A system for executing instructions using a plurality of register file segments for a processor, comprising:
a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks;
a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein resources of each partitionable engine are operable to be partitioned to instantiate a virtual core with partitioned resources of other partitionable engines, wherein communication between resources of each of said plurality of partitionable engines is supported by a global interconnection structure, and wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors; and
a plurality of register file segments coupled to the partitionable engines for providing data storage, wherein the global interconnection structure links each of the plurality of register file segments to each of the plurality of partitionable engines.

10. The system of claim 9 wherein the plurality of register file segments implement an execution mode wherein a subset of physical resources of each register file segment are allocated to support execution of a single logical thread of a logical core.

11. The system of claim 10 , wherein each register file segment implements a portion of a plurality of logical cores.

12. The system of claim 9 , wherein the plurality of register file segments implement an execution mode wherein physical resources of each register file segment are dynamically allocated in accordance with an adjustable threshold to support execution of a single logical thread of a single logical core.

13. The system of claim 12 , wherein the plurality of register file segments implement a portion of a plurality of logical cores.

14. The system of claim 9 , wherein the plurality of register file segments implement an execution mode wherein the set of physical resources of each register file segment are allocated to support execution of a single logical thread.

15. The system of claim 9 , wherein each register file segment further comprises a common partition scheduler, an operand and result buffer and a threaded register file.

16. The system of claim 9 , wherein the global interconnection structure comprises a routing matrix operable to allow the plurality of partitionable engines to access data stored at any point in the plurality of register file segments.

17. A processor for executing instructions using a plurality of register file segments, comprising:
a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler allocates incoming the instruction sequence into a plurality of code segments of instructions, and generates a plurality of inheritance vectors describing interdependencies between instructions of the code segments;
a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines wherein resources of each partitionable engine are operable to be partitioned to instantiate a virtual core with partitioned resources of other partitionable engines, wherein communication between resources of each of said plurality of partitionable engines is supported by a global interconnection structure, and wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors;
a plurality execution units coupled to the global front scheduler for executing the code segments in accordance with respective inheritance vectors; and
a plurality of register file segments coupled to the execution units for providing data storage, wherein the global interconnection structure links each of the plurality of register file segments to each of the plurality of execution units.

18. The processor of claim 17 wherein the plurality of register file segments implement an execution mode wherein a subset of physical resources of each register file segment are allocated to support execution of a single logical thread of a logical core.

19. The processor of claim 18 , wherein each register file segment implements a portion of a plurality of logical cores.

20. The processor of claim 17 , wherein the plurality of register file segments implement an e

Assignees

• Abdallah Mohammad
• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F13/1657

  Access to multiple memories · CPC title

• G06F2212/282

  Partitioned cache · CPC title