Processor core arrangement, computing system and methods for designing and operating a processor core arrangement

Patent metadata

Field	Value
Publication number	US-9841977-B2
Application number	US-201214646988-A
Country	US
Kind code	B2
Filing date	Nov 22, 2012
Priority date	Nov 22, 2012
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

First claim

The invention claimed is:

1. A method of designing a processor core arrangement, the method comprising:
operating a processor core arrangement, or simulating the processor core arrangement, with a first processor core having a SRPG (state retention power gate) feature in an operation in said operating or a simulation in said simulating, to determine a combined leakage of the first processor core and a second processor core, wherein
the processor core arrangement comprises a first processor core configured to operate at a first operation frequency and having an associated first leakage, and the second processor core configured to operate at a second operation frequency that is lower than the first operation frequency and having an associated second leakage that is lower than the associated first leakage, and
the processor core arrangement is configured to switch from the first processor core to the second processor core and vice versa;

choosing said combined leakage as a reference leakage;
omitting or deactivating said SRPG feature of said first processor core; and
setting said second operation frequency such that the combined leakage of said first processor core and said second processor core, with said SRPG feature omitted or deactivated, is substantially equal to said reference leakage.

2. The method of claim 1 , wherein the first operation frequency is at least double the second operation frequency.

3. The method of claim 1 , wherein the second operation frequency is at least a quarter or a third or a half of the first operation frequency.

4. The method of claim 1 , further comprising:
implementing the first processor core and the second processor core on one of a same substrate, a same die, a same chip, or as parts of a same integrated circuit.

5. The method of claim 1 , wherein the first processor core is operable in a burst mode.

6. The method of claim 1 , further comprising:
arranging the first processor core and the second processor core to utilize or take over state information of the respective other processor core when switching between the first processor core and the second processor core.

7. The method of claim 1 , wherein the first processor core and the second processor core have a same architecture type.

8. The method of claim 1 , wherein said simulation comprises:
switching between said first processor core and said second processor core depending on a computational load.

Assignees

• Rozen Anton
• Priel Michael
• Smolyansky Leonid
• Sofer Sergey
• Nxp Usa Inc

Inventors

• Rozen Anton
• Priel Michael
• Smolyansky Leonid
• Sofer Sergey

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F9/30189 Primary

  according to execution mode, e.g. mode flag · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F2115/10

  Processors · CPC title