Apparatus and method for handling registers in pipeline processing

Patent metadata

Field	Value
Publication number	US-9841957-B2
Application number	US-201615132815-A
Country	US
Kind code	B2
Filing date	Apr 19, 2016
Priority date	May 7, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An apparatus stores a program including a description of loop processing of iterating a plurality of instructions, and rearranges an execution sequence of the plurality of instructions in the program such that the loop processing is pipelined by software pipeline. The apparatus inserts an instruction to use a register for single instruction multiple data (SIMD) extension instruction, into the description of the loop processing in the program.

First claim

What is claimed is:

1. An apparatus comprising:
a memory configured to store a program including a description of loop processing of iterating a plurality of instructions; and
a processor coupled to the memory, configured to:
rearrange an execution sequence of the plurality of instructions in the program such that the loop processing is pipelined by software pipeline,
set a first register as a load destination of data in a load instruction of the plurality of instructions, and
insert a shift instruction to shift a data row in a storage area to left, into the description of the loop processing in the program, the data row being acquired by combining the first register with a right side of a second register for single instruction multiple data (SIMD) extension instruction,

wherein, for each of a plurality of iterations of the pipelined loop processing, the processor
loads data into the first register according to the load instruction, and
shifts the data row in the storage area acquired by combining the first register with the right side of the second register to left according to the shift instruction, and

wherein after each of the plurality of iterations of the pipelined loop processing is performed, the processor refers to data at a head of the second register.

2. The apparatus of claim 1 , wherein
in a case where a number of pieces of data simultaneously held as a result of pipelining is N where N is an integer of 2 or more, the processor sets a shift amount per shift instruction such that data loaded into the first register moves to the head of the second register by N shifts.

3. The apparatus of claim 1 , wherein
the processor determines whether a same number of registers as a number of pieces of data that are simultaneously held are available when the software pipeline is achieved by register renaming, and
when insufficient number of registers are available, the processor performs the setting of the first register as the load destination of data in the load instruction, and the inserting of the shift instruction.

4. A method comprising:
providing, by a processor, a program including a description of loop processing of iterating a plurality of instructions;
rearranging, by the processor, an execution sequence of the plurality of instructions such that the loop processing is pipelined by software pipeline;
setting, by the processor, a first register as a load destination of data in a load instruction of the plurality of instructions;
inserting, by the processor, a shift instruction to shift a data row in a storage area to left, into the description of the loop processing in the program, the data row being acquired by combining the first register with a right side of a second register for single instruction multiple data SIMD extension instruction;
for each of a plurality of iterations of the pipelined loop processing, loading, by the processor, data into the first register according to the load instruction and shifting the data row in the storage area acquired by combining the first register with the right side of the second register to left according to the shift instruction; and
after each of the plurality of iterations of the pipelined loop processing is performed, referring, by the processor, to data at a head of the second register.

5. A non-transitory, computer-readable recording medium having stored therein a program causing a computer to execute a process:
providing a program including a description of loop processing of iterating a plurality of instructions;
rearranging an execution sequence of the plurality of instructions such that the loop processing is pipelined by software pipeline;
setting a first register as a load destination of data in a load instruction of the plurality of instructions;
inserting a shift instruction to shift a data row in a storage area to left, into the description of the loop processing in the program, the data row being acquired by combining the first register with a right side of a second register for single instruction multiple data SIMD extension instruction;
for each of a plurality of iterations of the pipelined loop processing, loading data into the first register according to the load instruction and shifting the data row in the storage area acquired by combining the first register with the right side of the second register to left according to the shift instruction; and
after each of the plurality of iterations of the pipelined loop processing is performed, referring to data at a head of the second register.

6. A non-transitory, computer-readable recording medium having stored therein a program causing a computer to execute a process:
providing a program including a description of loop processing of iterating a plurality of instructions;
executing pipelined loop processing of iterating the plurality of instructions by software pipeline;
setting a first register as a load destination of data in a load instruction of the plurality of instructions;
inserting a shift instruction to shift a data row in a storage area to left, into the description of the loop processing in the program, the data row being acquired by combining the first register with a right side of a second register for single instruction multiple data SIMD extension instruction;
in each iteration of the pipelined loop processing, loading data into the first register according to the load instruction and shifting the data row in the storage area acquired by combining the first register with the right side of the second register to left according to the shift instruction; and
after each of the plurality of iterations of the pipelined loop processing is performed, referring to data at a head of the second register.

Assignees

• Fujitsu Ltd

Inventors

• Kamatsuka Shun

Classifications

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30138

  Extension of register space, e.g. register cache · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F8/453

  Data distribution · CPC title