Method for resetting an electronic device having independent device domains

Patent metadata

Field	Value
Publication number	US-9841795-B2
Application number	US-201414492711-A
Country	US
Kind code	B2
Filing date	Sep 22, 2014
Priority date	Sep 22, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

First claim

The invention claimed is:

1. A method for resetting an electronic device having independent device domains, the method comprising:
receiving signals indicating reset events from at least one reset source, wherein each reset event is indicative of at least one condition met which causes a reset to occur and wherein each reset event comprises one reset event selected from a group consisting of a power glitch reset event, tamper detect reset event, an open circuit error reset event, and an Error Correction Coding (ECC) error reset event;
capturing the reset events;
changing dynamically a reset control flow to reset one or more of the device domains of said electronic device depending on the sequence of captured reset events;
assigning a time stamp to the captured reset events, and
determining a time difference between captured reset events is determined on the basis of the assigned time stamps.

2. The method according to claim 1 ,
wherein the reset control flow to reset said device domains is further changed dynamically depending on at least one selected from a group consisting of the time duration of the captured reset events and a determined time difference between the occurrence of the captured reset events.

3. The method according to claim 1 ,
wherein the reset control flow to reset said device domains is further changed dynamically depending on types of the captured reset events.

4. The method according to claim 1 ,
wherein the reset control flow to reset said device domains is further changed dynamically depending on at least one selected from a group consisting of an operation mode of the respective device domain and the operation mode of the overall electronic device.

5. The method according to claim 1 , further comprising at least one of
receiving an internal control signal generated by a control unit or an electronic device; and
receiving an external control signal received by said electronic device,
wherein the reset control flow to reset said device domains is further changed dynamically in response to at least one of the internal control signal and the external control signal.

6. The method according to claim 1 ,
wherein the reset events comprise at least one selected from a group consisting of:
internal reset events generated by internal reset sources of said electronic device and
external reset events received from external reset sources connected to said electronic device.

7. A method for resetting an electronic device having independent device domains, the method comprising:
receiving signals indicating reset events from at least one reset source, wherein each reset event is indicative of at least one condition met which causes a reset to occur;
capturing the reset events;
changing dynamically a reset control flow to reset one or more of the device domains of said electronic device depending on the sequence of captured reset events, wherein the reset events provided by the different reset sources are captured and applied to a reset state control circuit of said electronic device having a capturing unit that captures the reset events and a reset shaping logic which changes dynamically the reset control flow to reset the device domains of said electronic device in response to the captured reset events, and wherein device domains reset by said reset shaping logic are held in a reset state during reset phases, wherein the time duration of the reset phases depends on at least one selected from a group consisting of the sequence order of the captured reset events, the time duration of the captured reset events, the types of the captured reset events, a current operation state, and a current operation condition of the device domains of said electronic device, and wherein a time stamp is assigned to the captured reset events and wherein determining a time difference between captured reset events is determined on the basis of the assigned time stamps.

8. The method according to claim 7 ,
wherein the reset shaping logic of said reset state control circuit changes dynamically the reset control flow to reset the device domains depending on at least one selected from a group consisting of a sequence order of the captured reset events, a time duration of the captured reset events, the types of the captured reset events, ongoing operation modes of the device domains, the current operation mode of the overall electronic device, internal control signals generated by a control unit of the electronic device, and external control signals received by the electronic device.

9. The method according to claim 7 ,
wherein the reset events provided by the different reset sources are applied in parallel to the capturing unit of said reset state control circuit comprising a masking unit which masks the applied reset events.

10. A reset state control circuit adapted to reset independent device domains of an electronic device,
said reset state control circuit comprising:
one or more inputs adapted to receive signals indicating reset events from at least one reset source, wherein each reset event is indicative of at least one condition met which causes a reset to occur, and wherein each reset event comprises one reset event selected from a group consisting of a power glitch reset event, tamper detect reset event, an open circuit error reset event, and an Error Correction Coding (ECC) error reset event;
a capturing unit adapted to capture the reset events, wherein the capturing unit is configured to assign a time stamp to the captured reset events and wherein determining a time difference between captured reset events is determined on the basis of the assigned time stamps; and
a reset shaping logic adapted to change dynamically a reset control flow to reset one or more device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

11. The reset state control circuit according to claim 10 ,
wherein the capturing unit comprises capturing blocks adapted to capture at least one of internal reset events received from internal reset sources and external reset events received from external reset sources.

12. The reset state control circuit according to claim 11 ,
wherein the reset sources are reset controllers provided for independent device domains of said electronic device.

13. The reset state control circuit according to claim 10 ,
wherein the reset shaping logic is adapted to change dynamically the reset control flow to reset device domains depending on at least one selected from a group consisting of a sequence order, a time duration of the captured reset events, the types of the captured reset events, current operation modes of the device domains, the current operation mode of the overall electronic device, internal control signals generated by a control unit of the electronic device, and external control signals received by said electronic device.

14. The reset state control circuit according to claim 10 ,
wherein the reset shaping logic is a programmable circuit or formed by a hardwired circuit.

15. An electronic device comprising at least one independent device domain and a reset control circuit according to claim 10 .

16. A system on chip comprising an integrated reset state control circuit according to claim 10 .

Assignees

• Culshaw Carl
• Gupta Sunny
• Luedeke Thomas Henry
• Sakalley Deboleena
• Nxp Usa Inc

Inventors

• Culshaw Carl
• Gupta Sunny
• Luedeke Thomas Henry
• Sakalley Deboleena

Classifications

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F1/24 Primary

  Resetting means · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F2201/835

  Timestamp · CPC title