Thin-film transistor array substrate and liquid crystal display panel

US9841630B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9841630-B2
Application numberUS-201514908115-A
CountryUS
Kind codeB2
Filing dateSep 8, 2015
Priority dateAug 17, 2015
Publication dateDec 12, 2017
Grant dateDec 12, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A thin-film transistor array substrate and a liquid crystal display panel are provided. The thin-film transistor array substrate includes a substrate, a thin-film transistor array, a color resisting layer and an alignment film The substrate includes a first surface and a second surface opposing to each other. The first surface has a revealing region and a non-revealing region surrounding the revealing region. The thin-film transistor array is arranged on the first surface of the substrate. The color resisting layer is arranged on the thin-film transistor array and has a trench located correspondingly to the non-revealing region. The alignment film is arranged on the color resisting layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin-film transistor array substrate, comprising: a substrate comprising a first surface and a second surface opposing to each other, the first surface having a revealing region and a non-revealing region surrounding the revealing region; a thin-film transistor array arranged on the first surface of the substrate; a color resisting layer which is arranged on the thin-film transistor array and comprises a trench located correspondingly to the non-revealing region; and an alignment film arranged on the color resisting layer. 2. The thin-film transistor array substrate according to claim 1 , wherein the color resisting layer comprises at least one trench. 3. The thin-film transistor array substrate according to claim 1 , wherein the color resisting layer comprises a plurality of trenches that are parallel with each other. 4. The thin-film transistor array substrate according to claim 1 , wherein the color resisting layer comprises a plurality of trenches that are formed in a grid pattern. 5. A liquid crystal display panel, comprising a thin-film transistor array substrate which comprises: a first substrate comprising a first surface and a second surface opposing to each other, the first surface having a revealing region and a non-revealing region surrounding the revealing region; a thin-film transistor array arranged on the first surface of the first substrate; a color resisting layer which is arranged on the thin-film transistor array and comprises a first trench located correspondingly to the non-revealing region; and a first alignment film arranged on the color resisting layer. 6. The liquid crystal display panel according to claim 5 , wherein the color resisting layer comprises at least one first trench. 7. The liquid crystal display panel according to claim 5 , wherein the color resisting layer comprises a plurality of first trenches that are parallel with each other. 8. The liquid crystal display panel according to claim 5 , wherein the color resisting layer comprises a plurality of first trenches that are formed in a grid pattern. 9. The liquid crystal display panel according to claim 5 further comprising a second substrate, the second substrate comprising a third surface and a fourth surface opposing to each other, the third surface which is closer to the first surface in comparison with the fourth surface having a black matrix layer, the black matrix layer having a second trench opposing to the first trench. 10. The liquid crystal display panel according to claim 9 , wherein the second trench faces directly to the first trench or interlaces with the first trench.

Assignees

Inventors

Classifications

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

  • Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

  • Physics · mapped topic

  • G02F1/1337Primary

    Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

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What does patent US9841630B2 cover?
A thin-film transistor array substrate and a liquid crystal display panel are provided. The thin-film transistor array substrate includes a substrate, a thin-film transistor array, a color resisting layer and an alignment film The substrate includes a first surface and a second surface opposing to each other. The first surface has a revealing region and a non-revealing region surrounding the re…
Who is the assignee on this patent?
Shenzhen China Star Optoelect, Shenzhen China Star Optoelect
What technology area does this patent fall under?
Primary CPC classification G02F1/133707. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).