Semiconductor apparatus, solid-state image sensing apparatus, and camera system

Patent metadata

Field	Value
Publication number	US-9838626-B2
Application number	US-201715630608-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Oct 21, 2011
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.

First claim

The invention claimed is:

1. An imaging device comprising:
a first substrate including:
a plurality of pixels, a pixel of the plurality of pixels being configured to output an analog signal, and
a plurality of signal lines, a signal line of the plurality of signal lines being coupled to the pixel; and

a second substrate including:
a plurality of comparators, a comparator of the plurality of comparators being coupled to the first signal line and including:
a first amplifier having a first transistor configured to receive a signal based on the analog signal, a second transistor configured to receive a reference signal, and an output node coupled to the first transistor,
a second amplifier having an input transistor configured to receive an output signal from the output node, and
a capacitor coupled the output node and the input transistor.

2. The imaging device according to claim 1 , wherein the capacitor is disposed between the output node and second amplifier.

3. The imaging device according to claim 1 , wherein a gate of the input transistor is coupled to the capacitor.

4. The imaging device according to claim 1 , wherein the first transistor and the second transistor have a first conductivity type.

5. The imaging device according to claim 4 , wherein the input transistor has a second conductivity type.

6. The imaging device according to claim 1 , wherein the capacitor is coupled between the first amplifier and the second amplifier.

7. The imaging device according to claim 1 , wherein the second amplifier has an input node coupled to the capacitor.

8. The imaging device according to claim 1 , wherein a first terminal of the input transistor is configured to receive a predetermined voltage.

9. The imaging device according to claim 8 , wherein a second terminal of the input transistor is coupled to the capacitor.

10. The imaging device according to claim 9 , wherein the predetermined voltage is a power source voltage.

11. The imaging device according to claim 1 , wherein a gate of the input transistor is configured to receive an output signal from the output node.

12. An imaging device comprising:
a first substrate including:
a pixel array unit including a plurality of pixels, a pixel of the plurality of pixels being configured to receive an incident light and output an analog signal, and
a plurality of signal lines, a signal line of plurality of signal lines being coupled to the pixel; and

a second substrate including:
a plurality of comparators, and
a plurality of counters,

wherein a comparator of the plurality of comparators includes a first amplifier, a second amplifier, and a capacitor,
wherein the first amplifier receives a reference signal and the analog signal,
wherein the capacitor is coupled to the first amplifier and the second amplifier, and
wherein the second amplifier is coupled to a counter of the plurality of counters.

13. The imaging device according to claim 12 , wherein the first amplifier is configured to compare the reference signal and the analog signal.

14. The imaging device according to claim 12 , wherein the pixel is coupled to at least one selected from a floating diffusion, a reset transistor, an amplification transistor, and/or a selection transistor.

15. The imaging device according to claim 12 , wherein the first amplifier includes a first transistor and a second transistor, a gate of the first transistor being configured to receive the reference signal and a gate of the second transistor being configured to receive the analog signal.

16. The imaging device according to claim 12 , wherein the second amplifier includes a third transistor, a gate of the third transistor being configured to receive an output signal from the first amplifier.

17. The imaging device according to claim 16 , wherein the capacitor is coupled the gate of the third transistor and one of a drain or a source of the third transistor.

18. The imaging device according to claim 12 , wherein the pixel includes a photodiode and a transfer transistor.

19. The imaging device according to claim 12 , wherein the first substrate and the second substrate are bonded to each other.

20. The imaging device according to claim 12 , wherein the second substrate includes at least a part of a control circuit.

21. An imaging device comprising:
a first substrate including:
a plurality of pixels, a pixel of the plurality of pixels being configured to output an analog signal, and
a plurality of signal lines, a signal line of the plurality of signal lines being coupled to the pixel; and

a second substrate including:
a plurality of comparators, a comparator of the plurality of comparators being coupled to the signal line and including:
a first circuit including a first transistor configured to receive a signal based on the analog signal, a second transistor configured to receive a reference signal, and an output node coupled to the first transistor,
a second circuit including an input transistor configured to receive an output signal from the output node, and
a capacitor coupled the output node and the input transistor.

22. The imaging device according to claim 21 , wherein the capacitor is disposed between the output node and the second amplifier.

23. The imaging device according to claim 21 , wherein a gate of the input transistor is coupled to the capacitor.

24. The imaging device according to claim 21 , wherein the first transistor and the second transistor have a first conductivity type.

25. The imaging device according to claim 24 , wherein the input transistor has a second conductivity type.

26. The imaging device according to claim 21 , wherein the capacitor is coupled between the first amplifier and the second amplifier.

27. The imaging device according to claim 21 , wherein the second amplifier has an input node coupled to the capacitor.

28. The imaging device according to claim 21 , wherein a first terminal of the input transistor configured to receive a predetermined voltage.

29. The imaging device according to claim 28 , wherein a second terminal of the input transistor is coupled to the capacitor.

30. The imaging device according to claim 29 , wherein the predetermined voltage is a power source voltage.

Assignees

• Sony Corp

Inventors

• Nagai Toshiaki
• Koseki Ken
• Ueno Yosuke
• Suzuki Atsushi

Classifications

• H04N25/76 Primary

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/65 Primary

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N23/54

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title