Integrated circuit, code generating method, and data exchange method

Patent metadata

Field	Value
Publication number	US-9838389-B2
Application number	US-201414335957-A
Country	US
Kind code	B2
Filing date	Jul 21, 2014
Priority date	Sep 27, 2013
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

First claim

What is claimed is:

1. An integrated circuit, comprising:
at least one first input/output end;
at least one current path, connected with the first input/output end;
at least one control end, disposed above the at least one current path, configured to apply a plurality of control end voltages on the at least one current path;
at least one second input/output end, connected with the current path; and
at least one sense-amplifier, connected with the at least one second input/output end, configured to sense the electric current from the at least one second input/output end and identify the threshold voltage according to one of the control end voltages and the electric current;
wherein at least one current adjusting element is disposed in the at least one current path to adjust an electrical current.

2. The integrated circuit of claim 1 , wherein the at least one current adjusting element comprises at least one dopant ion, and at least either the width or the thickness of the current path are defined according to the de Broglie length (DBL), and the length of the current path is longer than the width of the current path.

3. The integrated circuit of claim 1 , wherein the at least one current adjusting element comprises at least one grain boundary.

4. The integrated circuit of claim 3 , wherein the length of the current path is between an average grain width of the current path and three times the average grain width of the current path.

5. The integrated circuit of claim 3 , wherein the thickness of the current path is less than an average grain width of the current path.

6. The integrated circuit of claim 3 , wherein the grain boundary is located closer to one of the at least one first input/output end and the at least one second input/output end.

7. The integrated circuit of claim 3 , further comprising:
a processing circuit, configured to categorize each threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each threshold voltages at an address in a mapping table.

8. An integrated circuit, comprising:
a plurality of semiconductor cells, each semiconductor cell being configured to represent an address in a mapping table and comprising a first input/output end, a second input/output end, a current path and a control end, wherein at least one current adjusting element is disposed in at least one of the current paths to adjust an electrical current;
a plurality of sense-amplifiers, each connected to the second input/output end and being configured to sense an electric current from the second input/output end and identify the threshold voltage of the corresponding semiconductor cell; and
a processing circuit, configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

9. The integrated circuit of claim 8 , wherein the at least one current adjusting element comprises at least one dopant ion, and at least either the width or the thickness of the current paths are defined according to the de Broglie length (DBL), and the length of the current paths is longer than the width of the current path.

10. The integrated circuit of claim 8 , wherein the at least one current adjusting element comprises at least one grain boundary.

11. The integrated circuit of claim 10 , wherein the length of the current path is between an average grain width of the current path and three times the average grain width of the current path.

12. The integrated circuit of claim 10 , wherein the thickness of the current path is less than an average grain width of the current path.

13. The integrated circuit of claim 10 , wherein the grain boundary is located closer to one of the at least one first input/output end and the at least one second input/output end.

14. The integrated circuit of claim 10 , further comprising:
a common first input/output end line, electrically connecting the first input/output ends of the semiconductor cells; and
a common word line, electrically connecting the control ends of the semiconductor cells.

15. The integrated circuit of claim 10 , wherein the semiconductor cells comprise:
a semiconductor substrate;
a plurality of Fin layers, vertically fabricated on the semiconductor substrate, wherein the current paths are formed on the top of the Fin layer, and the first input/output ends and the second input/output ends are disposed respectively at an end and another end of a Fin layer and connected with the current paths; and
a plurality of dielectric layers, disposed on the plurality of Fin layers, wherein the control ends cover the dielectric layers.

16. The integrated circuit of claim 15 , wherein the dielectric layers further extend into the spaces between the Fin layers, and the control ends further surround the dielectric layers.

17. The integrated circuit of claim 10 , wherein the first input/output ends, the current paths and the second input/output ends form a plurality of nano-wires, and the control ends further surround the nano-wires with a plurality of dielectric layers in between.

18. The integrated circuit of claim 17 , wherein the diameter of the nano-wires is less than an average grain width of the current path.

19. The integrated circuit of claim 10 , wherein the semiconductor cells comprise:
a semiconductor substrate, configured to be as the first input/output ends;
a plurality of vertical pillars fabricated on the semiconductor substrate, configured to be as the current paths; and
a plurality of dielectric layers, surrounding the plurality of vertical pillars, the second input/output ends are disposed on a pillar, and the control ends surround the pillars with the dielectric layers in between.

20. The integrated circuit of claim 19 , wherein the diameter of the pillar is less than an average grain width of the current path.

21. A code generating method, adopted in an integrated circuit having a plurality semiconductor cells, each of the semiconductor cells comprising a first input/output end, a second input/output end and a current path, the method comprising:
configuring each cell to represent an address in a mapping table;
determining a first read voltage and a reference current;
sensing an electric current from the second input/output end and identifying a threshold voltage of the corresponding semiconductor cell, wherein at least one current adjusting element is disposed in at least one of the current paths to adjust the electrical current;
categorizing each of the threshold voltages into a first state and a second state; and
marking each cell at the corresponding address of the mapping table according to the state of the threshold voltages.

22. The code generating method of claim 21 , wherein the at least one current adjusting element comprises at least one dopant ion, and either the width or the thickness of the current paths are defined according to the de Broglie length (DBL), and the length of the current paths is longer than the width of the current path.

23. The code generating method of claim 21 , wherein the at least one current adjusting element comprises at least one grain boundary.

24. The code generating method of claim 23 , wherein the step of categorizing each of the identified threshold voltages into the first state and the second sta

Assignees

• Phison Electronics Corp

Inventors

• Watanabe Hiroshi

Classifications

• H04L45/745

  Address table lookup; Address filtering · CPC title

• H04L63/0876 Primary

  based on the identity of the terminal or configuration, e.g. MAC address, hardware or software configuration or device fingerprint · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/42376

  Electricity · mapped topic

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title