Memory misalignment correction

Patent metadata

Field	Value
Publication number	US-9838197-B2
Application number	US-201615094618-A
Country	US
Kind code	B2
Filing date	Apr 8, 2016
Priority date	Apr 8, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.

First claim

The invention claimed is:

1. A system for a phase shift keying receiver, said system comprising:
an analog front end for receiving an analog demodulated signal having a preamble portion and for generating a digital register input signal including a received preamble portion and comprising a number of symbols, each symbol having phase information;
a finite state machine for selecting a memory address of the demodulated signal based on a value of the symbols of the received preamble portion;
a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address and comprising a number of symbols, each symbol having preamble phase information; and
a memory alignment module configured to compare the phase information of the symbols of the preamble portion with the preamble phase information to check that the preamble portion of the register input signal aligns with the selected preamble memory output.

2. The system of claim 1 , wherein the memory alignment module is configured to compare the phase information of the symbols of the preamble portion with the preamble phase information by determining and comparing a phase variance trend and/or a phase status of at least two symbols and preferably four symbols of the preamble portion with the phase variance trend and/or a phase status of a corresponding at least two symbols and preferably four symbols of the selected preamble memory output.

3. The system of claim 1 , wherein the memory alignment module directly compares the phase information between symbols of the preamble portion of two or more received symbols and the preamble phase information between corresponding symbols of two or more received symbols of the selected preamble memory output.

4. The system of claim 1 , wherein the memory alignment module provides a memory alignment signal to the finite state machine if the phase information of symbols of the preamble portion and the preamble phase information of symbols of the selected preamble memory output do not match.

5. The system of claim 4 , wherein the memory alignment signal provides information about any misalignment between the phase information of the preamble portion and the preamble phase information of the selected preamble memory output to allow generation of a corrected preamble memory output.

6. The system of claim 4 , wherein the memory alignment signal provides information about the type of correction required to align the phase information of the preamble portion and the preamble phase information of the selected preamble memory output.

7. A memory alignment module for a phase shift keying receiver, said module comprising:
a comparator for receiving a register input signal having a preamble portion, wherein the comparator is configured to directly compare a phase value of received symbols of the preamble portion with a phase value of the previously received symbol of the preamble portion to determine phase information of the preamble portion;
an index comparator for receiving a preamble memory output with a memory address, wherein the index comparator is configured to directly compare a phase value of received symbols of the preamble memory output with a phase value of the previously received symbol of the preamble memory output to determine preamble phase information of the preamble memory output; and
an alignment comparator configured to compare the phase information and the preamble phase information to determine if they are aligned.

8. The module of claim 7 , wherein the phase information is the phase variance trend of two or more symbols of the preamble portion and/or the phase status of two or more received symbols of the preamble portion and the preamble phase information is the phase variance trend two or more symbols of the preamble memory output and/or the phase status of two or more preamble memory outputs.

9. The module of claim 7 , wherein the module is configured to generate a memory alignment signal if the phase information and the preamble phase information do not align.

10. The module of claim 9 , wherein the alignment comparator is configured to generate an address control signal if the phase information and the preamble phase information do not align.

11. The module of claim 10 , wherein the module further comprises an address control module configured to receive the address control signal and configured to determine an actual memory address of the preamble portion.

12. The module of claim 11 , wherein the module further comprises an address comparator configured to directly compare the actual memory address of the preamble portion with the memory address of the preamble memory output.

13. The module of claim 12 , wherein the address comparator is configured to:
generate the memory alignment signal if the actual memory address of the preamble portion and the memory address of the preamble memory output are misaligned; and
provide the memory alignment signal to a finite state machine so that the preamble memory output can be corrected.

14. The module of claim 7 , wherein the memory address of the preamble memory output is selected based on the initially received preamble portion of the register input signal.

15. A method of correcting memory misalignment in a phase shift keying receiver, said method comprising the steps of:
receiving an analog demodulated signal having a preamble portion;
generating a corresponding digital register input signal with a received preamble portion having phase information;
selecting a memory address of the demodulated signal based on the received preamble portion;
determining a preamble memory output having preamble phase information, based on the memory address from a database of all possible preambles contained within the demodulated signal; and
comparing the phase information of the preamble portion and the preamble phase information trend of the selected preamble memory output to check that the preamble memory output has been correctly generated.

Assignees

• Nxp Bv

Inventors

• Li Juhui
• Al-Kadi Ghiath
• Ciacci Massimo

Classifications

• H04L7/0016

  correction of synchronization errors · CPC title

• H04L27/2331 Primary

  wherein the received signal is demodulated using one or more delayed versions of itself · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L1/0079

  Formats for control data (H04L1/16 takes precedence; training sequences H04L25/00 and H04L27/00) · CPC title