Floating immittance emulator

Patent metadata

Field	Value
Publication number	US-9837987-B2
Application number	US-201615337414-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Nov 24, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.

First claim

We claim:

1. A floating immittance emulator circuit, comprising:
a first current feedback operational amplifier (CFOA) having first y-, x-, z-, and w-terminals;
a second CFOA having second y-, x-, z-, and w-terminals, the second z-terminal of the second CFOA being connected to the first z-terminal of the first CFOA, and the second y-terminal of the second CFOA being connected to the first y-terminal of the first CFOA;
a third CFOA having third y-, x-, z-, and w-terminals, the third x-terminal being connected to first x-terminal of the first CFOA and the second x-terminal of the second CFOA;
a first impedance having a first lead connected to the first y-terminal of the first CFOA and a second lead connected to the first z-terminal of the first CFOA;
a second impedance having a first lead connected to the first w-terminal of the first CFOA and a second lead connected to the third y-terminal of the third CFOA; and
a third impedance having a first lead connected to the third y-terminal of the third CFOA and a second lead connected to the third w-terminal of the third CFOA;
wherein the emulator circuit emulates immittance between a voltage v 1 applied to the first y-terminal of the first CFOA and a voltage v 2 applied to the second y-terminal of the second CFOA.

2. The floating immittance emulator according to claim 1 , wherein the first, second and third impedances comprise a resistance R 1 , a capacitance C 2 , and a resistance R 3 , respectively, the emulator simulating a lossless negative inductance.

Assignees

• Univ King Fahd Pet & Minerals

Inventors

• Abuelma'Atti Muhammad Taher
• Dhar Sagar Kumar

Classifications

• H03H11/53

  simulating resistances; simulating resistance multipliers · CPC title

• H03H11/481

  Simulating capacitances · CPC title

• H03H11/485 Primary

  Simulating inductances using operational amplifiers · CPC title

• H03H2011/0477

  using current feedback operational amplifiers · CPC title

• H03H11/1217

  using a plurality of operational amplifiers (H03H11/1204 takes precedence; parallel-T filters H03H11/1295) · CPC title