Oscillation circuit

Patent metadata

Field	Value
Publication number	US-9837960-B2
Application number	US-201615272695-A
Country	US
Kind code	B2
Filing date	Sep 22, 2016
Priority date	Sep 30, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Provided is an oscillation circuit that can limit a maximum value and a minimum value of a frequency even when some troubles are caused in a V/I conversion circuit. The oscillation circuit includes a current controlled oscillator configured to oscillate based on an input current, and a current limiting circuit configured to: compare the input current with a first constant current and with a second constant current; limit, when the input current reaches the first constant current, a maximum current value of the input current with a transistor arranged on a path of the input current; and limit, when the input current is lowered to the second constant current, a minimum current of the input current through addition of current on the path of the input current by a transistor arranged in parallel with the path of the input current.

First claim

What is claimed is:

1. An oscillation circuit, comprising:
a current source circuit configured to generate a second current based on a first current flowing through a first current path between a power supply terminal and a current input terminal; and
a current controlled oscillator configured to oscillate based on the second current, the current source circuit comprising:
a first PMOS transistor in the first current path, and including a gate and a drain connected to each other;
a second PMOS transistor forming a current mirror circuit with the first PMOS transistor, the second PMOS transistor configured to cause the second current to flow therethrough;
a third PMOS transistor forming a current mirror circuit with the first PMOS transistor;
a constant current source connected to a drain of the third PMOS transistor; and
a fourth PMOS transistor configured to limit a current value of the first current, and including a gate controlled by a voltage of the drain of the third PMOS transistor.

2. An oscillation circuit according to claim 1 , wherein the fourth PMOS transistor is connected to the power supply terminal and to the current input terminal in the first current path and is configured to limit a maximum current value of the first current.

3. An oscillation circuit according to claim 1 , wherein the fourth PMOS transistor is in second current path between the current input terminal and a ground terminal and is connected to the current input terminal and the ground terminal and is configured to limit a minimum current value of the first current.

4. An oscillation circuit according to claim 2 , further comprising:
a fifth PMOS transistor forming a current mirror circuit with the first PMOS transistor;
a constant current source connected to a drain of the fifth PMOS transistor; and
a sixth transistor in a second current path between the current input terminal and a ground terminal,
wherein the sixth transistor is configured to limit a minimum current value of the first current.

5. An oscillation circuit according to claim 1 , further comprising a V/I conversion circuit configured to output a predetermined current based on a predetermined voltage,
wherein an output of the V/I conversion circuit is connected to the current input terminal.

6. An oscillation circuit according to claim 1 , further comprising:
a phase/frequency comparator circuit configured to receive a clock signal and output of the current controlled oscillator;
a charge pump circuit configured to receive output of the phase/frequency comparator circuit;
a capacitor connected to an output of the charge pump circuit;
an NMOS transistor including a drain connected to the current input terminal, and a gate configured to receive an output of the charge pump circuit; and
a resistor connected to a source of the NMOS transistor.

7. An oscillation circuit, comprising:
a current controlled oscillator configured to oscillate based on an input current; and
a current limiting circuit including a maximum current source, a minimum current source, an input terminal and a ground terminal, and configured to:
compare the input current with a first constant current and with a second constant current;
when the input current reaches the first constant current, limit a maximum current value of the input current with a transistor having a gate connected to the maximum current source in a path of the input current between the input terminal and the ground terminal; and
when the input current is lowered to the second constant current, limit a minimum current of the input current through addition of current on the path of the input current by a transistor having a gate connected to the minimum current source and in parallel with the path of the input current.

Assignees

• Sii Semiconductor Corp

Inventors

• Takada Kosuke

Classifications

• H03L1/00

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H03K3/0231 Primary

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title

• H03B5/1234 Primary

  and comprising means for varying the output amplitude of the generator (H03B5/1278 takes precedence) · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title