Apparatus and method for a low loss coupling capacitor

Patent metadata

Field	Value
Publication number	US-9837555-B2
Application number	US-201514687549-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Apr 15, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

First claim

What is claimed is:

1. A circuit structure for a coupling capacitor comprising:
a p-doped semiconductor substrate (Psub);
a deep n-doped semiconductor well (DNW) in the Psub, wherein the DNW is configured to be coupled to a first direct current (DC) bias;
a first p-doped semiconductor well (P well) in the DNW;
a first block of a p-doped semiconductor material extending from a surface of the first P well into the first P well, wherein the first block is a first source terminal;
a second block of the p-doped semiconductor material extending from the surface of the first P well into the first P well, wherein the second block is a first drain terminal, and wherein the first source terminal and the first drain terminal are configured to be coupled to a second DC bias;
an insulator block on the first P well between the first source terminal and the first drain terminal;
a block of conductor material on the insulator block between the first source terminal and the first drain terminal, wherein the block of conductor material is a first gate, wherein the first gate is configured to be coupled to a third DC bias, wherein the first DC bias is greater than the second DC bias, and wherein the second DC bias is greater than the third DC bias; and
a metal pattern comprising a plurality of layers of metal lines wherein the layers of metal lines are approximately parallel to the surface, and a plurality of vias through the metal lines and perpendicular to the metal lines, wherein the vias connect the metal lines to the first gate, the first source terminal, and the first drain terminal.

2. The circuit structure of claim 1 further comprising:
a second P well in the DNW;
a third block of the p-doped semiconductor material that serves as a second source terminal, the second source terminal extending from a surface of the second P well into the second P well;
a fourth block of the p-doped semiconductor material that serves as a second drain terminal, the second drain terminal extending from the surface of the second P well into the second P well;
a second insulator block on the second P well between the second source terminal and the second drain terminal; and
a second block of conductor material on the second insulator block that serves as a second gate, the second gate positioned between the second source terminal and the second drain terminal, wherein the vias further connect the metal lines to the second gate, the second source terminal, and the second drain terminal.

3. The circuit structure of claim 1 , wherein the metal lines are oriented approximately perpendicular to each other in consecutive layers of the metal pattern.

4. The circuit structure of claim 1 , wherein the metal lines in each layer of the metal pattern are approximately parallel.

5. The circuit structure of claim 1 , wherein the metal lines in each layer include alternating first lines and second lines, wherein the first lines are connected by the vias to the first gate, and wherein the second lines are connected by the vias to the first source terminal and the first drain terminal.

6. The circuit structure of claim 1 , wherein the DNW is more heavily doped than the first P well.

7. The circuit structure of claim 1 , wherein opposite end sidewalls of the first gate are adjacent to sidewalls of the first source terminal and the first drain terminal.

8. The circuit structure of claim 1 , wherein the metal lines in different layers of the metal pattern have different dimensions including at least one of different spacing, different width, different depth, and different length.

9. The circuit structure of claim 1 , wherein the metal lines in higher layers of the metal pattern from the surface have greater width and larger spacing than the metal lines in lower metal layers.

10. The circuit structure of claim 1 , wherein the first gate, the first source terminal and first drain terminal are connected to direct current (DC) biases, the Psub is grounded, and the DNW is connected to a power supply through a resistor.

11. The circuit structure of claim 1 , wherein the circuit structure further comprises:
a first n-doped semiconductor well (N well) in the Psub;
a first block of an n-doped semiconductor material extending from a surface of the first N well into the first N well, wherein the first block of an n-doped semiconductor material is a second source terminal;
a second block of the n-doped semiconductor material extending from the surface of the first N well into the first N well, wherein the second block of an n-doped semiconductor material is a second drain terminal;
a second insulator block on the first N well between the second source terminal and the second drain terminal;
a second block of conductor material on the second insulator block between the second source terminal and the second drain terminal, wherein the second block of conductor material is a second gate; and
wherein the vias further connect the metal lines to the second gate, the second source terminal, and the second drain terminal.

12. The circuit structure of claim 11 further comprising:
a second N well in the Psub;
a third block of the n-doped semiconductor material that serves as a third source terminal, the third source terminal extending from a surface of the second N well into the second N well;
a fourth block of the n-doped semiconductor material that serves as a third drain terminal, the third drain terminal extending from the surface of the second N well into the second N well;
a third insulator block on the second N well between the third source terminal and the third drain terminal; and
a third block of conductor material that serves as a third gate, the third gate positioned on the surface of the second N well between the third source terminal and the third drain terminal, wherein the vias further connect the metal lines to the third gate, the third source terminal, and the third drain terminal.

13. The circuit structure of claim 11 , wherein the metal lines are oriented approximately perpendicular to each other in consecutive layers of the metal pattern.

14. The circuit structure of claim 11 , wherein the metal lines in each layer of the metal pattern are approximately parallel.

15. The circuit structure of claim 11 , wherein the metal lines in each layer include alternating first lines and second lines, wherein the first lines are connected by the vias to the second gate, and wherein the second lines are connected by the vias to the second source terminal and the second drain terminal.

16. The circuit structure of claim 11 , wherein the metal lines in different layers of the metal pattern have different dimensions including at least one of different spacing, different width, different depth, and different length.

17. The circuit structure of claim 11 , wherein the metal lines in higher layers of the metal pattern from the surface have greater width and larger spacing than the metal lines in lower metal layers.

18. The circuit structure of claim 11 , wherein the second gate, the second source terminal and the second drain terminal are connected to direct current (DC) biases, and wherein the Psub is grounded.

19. A method for making a coupling capacitor structure, the method comprising:
forming a deep n-doped well (DNW) in a p-doped semiconductor substrate (Psub), wherein the DNW is operative at a first direct current (DC) bias;
forming a first p-doped semiconductor well (P well) in the DNW;
forming a first block of a p-doped semiconductor material extending from a surface of t

Assignees

• Futurewei Technologies Inc

Inventors

• Creed Brian
• Connell Lawrence
• Jaeger Kent
• Miller Matthew Richard

Classifications

• H01L29/66189

  Electricity · mapped topic

• H01L29/94

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/93 Primary

  Electricity · mapped topic

• H10D1/64 Primary

  Variable-capacitance diodes, e.g. varactors · CPC title