Method of modifying capping layer in semiconductor structure

Patent metadata

Field	Value
Publication number	US-9837504-B2
Application number	US-201514925657-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Oct 28, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method of fabricating the gate structure in a semiconductor device includes forming a gate dielectric layer over a semiconductor substrate. A capping layer is formed over the gate dielectric layer. The capping layer is treated with a first hydrogen plasma to form a first-treated capping layer. A gate electrode is formed over the first-treated capping layer. The method may further includes treating the first-treated capping layer with a nitrogen plasma.

First claim

What is claimed is:

1. A method of fabricating a gate structure in a semiconductor device, the method comprising:
forming a gate dielectric layer over a substrate;
forming a capping layer over the gate dielectric layer, and the capping layer comprising TiN, TaN, AlN, SiN, TiC, TaC, AlC, SiC, or a combination thereof;
treating the capping layer with a first hydrogen plasma to form a first-treated capping layer;
treating the first-treated capping layer with a first nitrogen plasma; and
forming a gate electrode over the first-treated capping layer.

2. The method of claim 1 , wherein the first nitrogen plasma is generated from a nitrogen-containing gas comprising NH 3 , N 2 or both.

3. The method of claim 1 , wherein the first hydrogen plasma has a power in a range of 250 to 2000 W.

4. The method of claim 1 , further comprising a dilution gas in the first hydrogen plasma.

5. The method of claim 1 , further comprising forming a first barrier layer over the capping layer and treating the first barrier layer with the first hydrogen plasma to form a first-treated first barrier layer.

6. The method of claim 5 , further comprising treating the first-treated first barrier layer with the first nitrogen plasma.

7. The method of claim 1 , further comprising forming a first barrier layer over the first-treated capping layer and treating the first barrier layer with a second hydrogen plasma to form a first-treated first barrier layer.

8. The method of claim 7 , further comprising treating the first-treated first barrier layer with a second nitrogen plasma.

9. The method of claim 1 , wherein treating the first-treated capping layer with the first nitrogen plasma comprises:
performing a nitriding process to the first-treated capping layer.

10. The method of claim 1 , wherein treating the first-treated capping layer with the first nitrogen plasma comprises:
diffusing nitrogen into the first-treated capping layer.

11. A method of modifying a capping layer in a semiconductor structure, the method comprising:
receiving an underlying structure;
forming a capping layer over the underlying structure, and the capping layer comprising TiN, TaN, AlN, SiN, TiC, TaC, AlC, SiC, or a combination thereof;
treating the capping layer with a first hydrogen plasma and a nonionized dilution gas to form a first-treated capping layer; and
treating the first-treated capping layer with a first nitrogen plasma.

12. The method of claim 11 , further comprising forming a first barrier layer over the capping layer and treating the first barrier layer with the first hydrogen plasma to form a first-treated first barrier layer.

13. The method of claim 12 , further comprising treating the first-treated first barrier layer with the first nitrogen plasma.

14. The method of claim 11 , further comprising forming a first barrier layer over the first-treated capping layer and treating the first barrier layer with a second hydrogen plasma to form a first-treated first barrier layer.

15. The method of claim 14 , further comprising treating the first-treated first barrier layer with a second nitrogen plasma.

16. A gate structure, comprising:
a substrate;
a gate dielectric layer over the substrate;
an oxygen-deficient capping layer having a surface sequentially treated with a hydrogen plasma and a nitrogen plasma, over the gate dielectric layer, and the oxygen-deficient capping layer comprising TiN, TaN, AlN, SiN, TiC, TaC, AlC, SiC, or a combination thereof; and
a gate electrode over the surface of the oxygen-deficient capping layer.

17. The gate structure of claim 16 , further comprising an oxygen-deficient first barrier layer over the oxygen-deficient capping layer.

18. The gate structure of claim 17 , further comprising an oxygen-deficient second barrier layer over the oxygen-deficient first barrier layer.

19. The gate structure of claim 16 , further comprising an oxygen-deficient first barrier layer between the oxygen-deficient capping layer and the gate electrode.

20. The gate structure of claim 18 , wherein the oxygen-deficient second barrier layer comprises Mo, Ru, Ti, Os, Re, Rh, Ir, Pt, Ta, In, Cd, Ag, Al, Nb, nitrides thereof, carbides thereof, or a combination thereof.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chun-Heng
• Liu Wayne
• Chen Liang-Yin
• Yu xiong-fei
• Chang Hui-Cheng

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/01302 Primary

  the insulator being formed after the semiconductor body, the semiconductor being silicon · CPC title

• H01L29/66636

  Electricity · mapped topic