III-nitride semiconductor structures with strain absorbing interlayers

Patent metadata

Field	Value
Publication number	US-9837495-B2
Application number	US-201514619942-A
Country	US
Kind code	B2
Filing date	Feb 11, 2015
Priority date	Mar 3, 2011
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a substrate;
a first transition body over said substrate, said first transition body having a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite said first surface;
a second transition body formed directly on said second surface of said first transition body, said second transition body having a smaller lattice parameter at a lower surface and a larger lattice parameter at an upper surface;
a III-Nitride semiconductor layer over said second transition body;
said first and second transition bodies reducing strain for said semiconductor structure, wherein said first lattice parameter is higher than said second lattice parameter.

2. The semiconductor structure of claim 1 , wherein said substrate is a non-III-Nitride substrate.

3. The semiconductor structure of claim 1 , wherein said III-Nitride semiconductor layer comprises a fabricated device.

4. The semiconductor structure of claim 3 , wherein said fabricated device is a high electron mobility transistor (HEMT).

5. The semiconductor structure of claim 1 , wherein said second transition body comprises a transition module including a superlattice.

6. The semiconductor structure of claim 5 , wherein said transition module comprises two or more interlayers.

7. The semiconductor structure of claim 5 , wherein said transition module comprises a lower interlayer at said lower surface of said second transition body, a middle interlayer and an upper interlayer at said upper surface of said second transition body.

8. The semiconductor structure of claim 1 , wherein said substrate is a group IV substrate.

9. The semiconductor structure of claim 1 , wherein said substrate is a silicon substrate.

10. A semiconductor structure comprising:
a non-III-Nitride substrate;
a strain absorbing layer;
a first transition body over said strain absorbing layer, said first transition body having a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite said first surface;
a second transition body formed directly on said second surface of said first transition body, said second transition body having a smaller lattice parameter at a lower surface and a larger lattice parameter at an upper surface;
a III-Nitride semiconductor layer over said second transition body;
said first and second transition layers reducing strain for said semiconductor structure, wherein said first lattice parameter is larger than said second lattice parameter.

11. The semiconductor structure of claim 10 , wherein said substrate is a non-III-Nitride substrate.

12. The semiconductor structure of claim 10 , wherein said III-Nitride semiconductor layer comprises a fabricated device.

13. The semiconductor structure of claim 10 , wherein said fabricated device is a high electron mobility transistor (HEMT).

14. The semiconductor structure of claim 10 , wherein said second transition body comprises a transition module including a superlattice.

15. The semiconductor structure of claim 14 , wherein said transition module comprises two or more interlayers.

16. The semiconductor structure of claim 14 , wherein said transition module comprises a lower interlayer at said lower surface of said second transition body, a middle interlayer and an upper interlayer at said upper surface of said second transition body.

17. The semiconductor structure of claim 10 , further comprising an intermediate layer comprising AlN formed between said strain absorbing layer and said first transition body.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Briere Michael A

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3254

  Graded layers · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3216

  Nitrides · CPC title