Array substrate with double-gate TFT, method of fabricating the same, and display device

Patent metadata

Field	Value
Publication number	US-9837480-B2
Application number	US-201514787396-A
Country	US
Kind code	B2
Filing date	Mar 18, 2015
Priority date	Nov 10, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

An array substrate, a method for fabricating the array substrate and a display device are described. The array substrate includes: a first gate electrode metal layer; a first gate insulation layer; an active layer on the first gate insulation layer; an etching barrier layer on the active layer; a source-drain metal layer including a source electrode and a drain electrode that contact with two sides of the active layer respectively; a second gate insulation layer on the source-drain metal layer; and a second gate electrode metal layer on the second gate insulation layer. The array substrate has an optimized TFT performance and a reduced gate line resistance, and light may be blocked from irradiating on the active layer, which is beneficial to restrain IR Drop, drifting of TFT threshold voltages or generation of a light-incurred leakage current on the active layer. Performance of the display device is improved.

First claim

The invention claimed is:

1. An array substrate, comprising:
a first gate electrode metal layer including a first gate electrode;
a first gate insulation layer on the first gate electrode metal layer;
an active layer that corresponds to the first gate electrode metal layer and is disposed on the first gate insulation layer;
an etching barrier layer on the active layer;
a source-drain metal layer comprising a source electrode and a drain electrode, wherein the source electrode and the drain electrode contact with two sides of the active layer respectively and are separated from each other on the etching barrier layer;
a second gate insulation layer on the source-drain metal layer; and
a second gate electrode metal layer on the second gate insulation layer, the second gate electrode metal layer including a second gate electrode,
wherein both a pattern of the first gate electrode and a pattern of the second gate electrode are simultaneously greater than a pattern of the active layer.

2. The array substrate according to claim 1 , wherein a position where the first gate electrode metal layer is formed on the array substrate corresponds to a position where the second gate electrode metal layer is formed on the array substrate.

3. The array substrate according to claim 1 , wherein the array substrate further comprises a connection electrode that electrically connects the first gate electrode metal layer with the second gate electrode metal layer.

4. The array substrate according to claim 3 , wherein the array substrate further comprises a through hole which runs through the first gate insulation layer, the etching barrier layer and the second gate insulation layer, and the connection electrode is disposed in the through hole and contacts with the first gate electrode metal layer and the second gate electrode metal layer.

5. The array substrate according to claim 1 , further comprising:
a passivation layer on the source-drain metal layer;
a planarization layer on the passivation layer; and
a metal electrode layer on the planarization layer, the metal electrode layer configured to connect to an anode of an organic light emitting diode.

6. A method for fabricating an array substrate, comprising:
forming a pattern comprising a first gate electrode metal layer on a base, the first gate electrode metal layer including a first gate electrode;
forming a pattern comprising a first gate insulation layer on the first gate electrode metal layer;
forming a pattern comprising an active layer on the first gate insulation layer;
forming an etching barrier layer on the active layer;
forming a pattern comprising a source-drain metal layer, wherein the source-drain metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode contact with two sides of the active layer respectively and are separated from each other on the etching barrier layer;
forming a pattern comprising a second gate insulation layer on the source-drain metal layer; and
forming a pattern comprising a second gate electrode metal layer on the second gate insulation layer, the second gate electrode metal layer including a second gate electrode,
wherein both a pattern of the first gate electrode and a pattern of the second gate electrode are simultaneously greater than a pattern of the active layer.

7. The method according to claim 6 , wherein a position where the first gate electrode metal layer is formed on the array substrate corresponds to a position where the second gate electrode metal layer is formed on the array substrate.

8. The method according to claim 7 , wherein the pattern comprising the first gate insulation layer, the pattern comprising the etching barrier layer and the pattern comprising the second gate insulation layer include a pattern that comprises a through hole corresponding to a same position on the array substrate; and
wherein the pattern comprising the second gate electrode metal layer further comprises a pattern comprising a connection electrode, and the connection electrode is disposed in the through hole and contacts with the first gate electrode metal layer and the second gate electrode metal layer.

9. The method according to claim 6 , wherein after forming the pattern comprising the second gate electrode metal layer on the second gate insulation layer, the method further comprises:
forming a pattern comprising a passivation layer;
forming a pattern comprising a planarization layer; and
forming a pattern comprising a metal electrode layer, wherein the metal electrode layer is configured to connect to an anode of an organic light emitting diode.

10. A display device, comprising the array substrate according to claim 1 .

11. The array substrate according to claim 2 , wherein the array substrate further comprises a connection electrode that electrically connects the first gate electrode metal layer with the second gate electrode metal layer.

12. The array substrate according to claim 11 , wherein the array substrate further comprises a through hole which runs through the first gate insulation layer, the etching barrier layer and the second gate insulation layer, and the connection electrode is disposed in the through hole and contacts with the first gate electrode metal layer and the second gate electrode metal layer.

13. The array substrate according to claim 2 , further comprising:
a passivation layer on the source-drain metal layer;
a planarization layer on the passivation layer; and
a metal electrode layer on the planarization layer, the metal electrode layer configured to connect to an anode of an organic light emitting diode.

14. The array substrate according to claim 3 , further comprising:
a passivation layer on the source-drain metal layer;
a planarization layer on the passivation layer; and
a metal electrode layer on the planarization layer, the metal electrode layer configured to connect to an anode of an organic light emitting diode.

15. The array substrate according to claim 4 , further comprising:
a passivation layer on the source-drain metal layer;
a planarization layer on the passivation layer; and
a metal electrode layer on the planarization layer, the metal electrode layer configured to connect to an anode of an organic light emitting diode.

16. The array substrate according to claim 2 , wherein the array substrate further comprises a through hole which runs through the first gate insulation layer, the etching barrier layer and the second gate insulation layer, and a connection electrode is disposed in the through hole and contacts with the first gate electrode metal layer and the second gate electrode metal layer.

17. The array substrate according to claim 1 , wherein the array substrate further comprises a through hole which runs through the first gate insulation layer, the etching barrier layer and the second gate insulation layer, and a connection electrode is disposed in the through hole and contacts with the first gate electrode metal layer and the second gate electrode metal layer.

18. The array substrate according to claim 1 , wherein the first gate electrode metal layer and the second gate electrode metal layer are connected to a common scan signal line.

19. The method according to claim 7 , wherein after forming the pattern comprising the second gate electrode metal layer on the second gate insulation layer, the method further comprises:
forming a pattern comprising a passivation layer;
forming a pattern comprising a planarization layer; and
form

Assignees

• Boe Technology Group Co Ltd

Inventors

• Gai Cuili
• Song Danna
• Zhang Baoxia

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L29/78678

  Electricity · mapped topic

• H01L29/78645

  Electricity · mapped topic

• H01L27/3272 Primary

  Electricity · mapped topic

• H01L27/3258

  Electricity · mapped topic