Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9837460-B2
Application number	US-201615363585-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Dec 28, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n − -type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n − -type semiconductor region, and a p − -type semiconductor region formed between the n − -type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n − -type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p − -type semiconductor region is lower than a net impurity concentration in the p-type well.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first semiconductor region having a first conductivity type and formed in a main surface of the semiconductor substrate;
a second semiconductor region having a second conductivity type different from the first conductivity type and formed in the first semiconductor region;
a first gate electrode formed over a first portion of the first semiconductor region which is located closer to a first side of the second semiconductor region in plan view via a first gate insulating film;
a third semiconductor region having the second conductivity type and formed in a second portion of the first semiconductor region which is located close to the main surface than the second semiconductor region;
a fourth semiconductor region having the first conductivity type and formed in a third portion of the first semiconductor region which is located between the second and third semiconductor regions; and
a fifth semiconductor region having the second conductivity type and formed in a fourth portion of the first semiconductor region which is located opposite to the second semiconductor region relative to the first gate electrode interposed therebetween in plan view,
wherein the first, second, third, and fourth semiconductor regions form a first photodiode,
wherein the first gate electrode and the fifth semiconductor region form a first transfer transistor which transfers charges generated in the first photodiode,
wherein a net impurity concentration in the second semiconductor region which is obtained by subtracting a concentration of an impurity having the first conductivity type from a concentration of an impurity having the second conductivity type is lower than a net impurity concentration in the third semiconductor region which is obtained by subtracting the first-conductivity-type impurity concentration from the second-conductivity-type impurity concentration, and
wherein a net impurity concentration in the fourth semiconductor region which is obtained by subtracting the second-conductivity-type impurity concentration from the first-conductivity-type impurity concentration is lower than a net impurity concentration in the first semiconductor region which is obtained by subtracting the second-conductivity-type impurity concentration from the first-conductivity-type impurity concentration.

2. The semiconductor device according to claim 1 ,
wherein a thickness of the third semiconductor region is smaller than a thickness of the second semiconductor region, and
wherein a thickness of the fourth semiconductor region is smaller than a thickness of the third semiconductor region.

3. The semiconductor device according to claim 1 ,
wherein the fourth semiconductor region contains a first impurity having the second conductivity type, and
wherein the first semiconductor region contains the first impurity at a concentration lower than a concentration of the first impurity in the fourth semiconductor region or does not contain the first impurity.

4. The semiconductor device according to claim 1 ,
wherein the first gate electrode is formed over the first portion of the first semiconductor region which is located close to the first side than the second semiconductor region in a first direction in plan view via the first gate insulating film, and
wherein the net impurity concentration in the fourth semiconductor region which is obtained by subtracting the second-conductivity-type impurity concentration from the first-conductivity-type impurity concentration is lower than a net impurity concentration in a fifth portion of the first semiconductor region which is obtained by subtracting the second-conductivity-type impurity concentration from the first-conductivity-type impurity concentration, the fifth portion facing the first gate electrode in a second direction perpendicular to the main surface and facing the fourth semiconductor region in the first direction.

5. The semiconductor device according to claim 1 ,
wherein the second semiconductor region is included in the third semiconductor region in plan view.

6. The semiconductor device according to claim 5 ,
wherein the second semiconductor region faces a sixth portion of the third semiconductor region which is located on the first side.

7. The semiconductor device according to claim 5 ,
wherein the first gate electrode is formed over the first portion of the first semiconductor region which is located close to the first side than the second semiconductor region in a third direction in plan view via the first gate insulating film, and
wherein the second semiconductor region faces a middle portion of the third semiconductor region in the third direction.

8. The semiconductor device according to claim 5 ,
wherein the second semiconductor region faces a seventh portion of the third semiconductor region which is located on a side opposite to the first side.

9. The semiconductor device according to claim 5 ,
wherein a plurality of the second semiconductor regions are formed in the first semiconductor region to be spaced apart from each other in plan view,
wherein a plurality of the fourth semiconductor regions are formed respectively in a plurality of the third portions of the first semiconductor region which are located between the third semiconductor region and the second semiconductor regions,
wherein the third semiconductor region is formed in the second portion of the first semiconductor region which is located closer to the main surface than the second semiconductor regions, and
wherein the second semiconductor regions are included in the third semiconductor region in plan view.

10. The semiconductor device according to claim 1 ,
wherein the first semiconductor region is formed in a first region of the semiconductor substrate which is close to the main surface,
the semiconductor device further comprising:
a sixth semiconductor region having the first conductivity type and formed in a second region of the semiconductor substrate which is close to the main surface;
a seventh semiconductor region having the second conductivity type and formed in the sixth semiconductor region;
a second gate electrode formed over an eighth portion of the sixth semiconductor region which is located close to a second side than the seventh semiconductor region in plan view via a second gate insulating film;
an eighth semiconductor region having the second conductivity type and formed in a ninth portion of the sixth semiconductor region which is located closer to the main surface than the seventh semiconductor region;
a ninth semiconductor region having the first conductivity type and formed in a tenth portion of the sixth semiconductor region which is located between the seventh and eighth semiconductor regions; and
a tenth semiconductor region having the second conductivity type and formed in an eleventh portion of the sixth semiconductor region which is located opposite to the seventh semiconductor region relative to the second gate electrode interposed therebetween in plan view,
wherein the sixth, seventh, eighth, and ninth semiconductor regions form a second photodiode,
wherein the second gate electrode and the tenth semiconductor region form a second transfer transistor which transfers charges generated in the second photodiode,
wherein the first photodiode receives first incident light and converts the first incident light to charges,
wherein the second photodiode receives second incident light having a wavelength shorter than a wavelength of the first incident light and converts the second incident light to charges,
wherein a net impurity concentration in the seventh semiconduct

Assignees

• Renesas Electronics Corp

Inventors

• Takeuchi Yosuke
• Kunikiyo Tatsuya

Classifications

• H01L27/14698

  Electricity · mapped topic

• H01L27/14612

  Electricity · mapped topic

• H01L27/14621

  Electricity · mapped topic

• H01L27/14645 Primary

  Electricity · mapped topic

• H01L31/1105

  Electricity · mapped topic