Method for producing hybrid substrates, and hybrid substrate

Patent metadata

Field	Value
Publication number	US-9837301-B2
Application number	US-201314416724-A
Country	US
Kind code	B2
Filing date	Jul 18, 2013
Priority date	Jul 25, 2012
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method for producing hybrid substrates which can be incorporated into a semiconductor production line involves: forming an ion-injection region ( 3 ) by injecting ions from the surface of a silicon substrate ( 1 ); adhering the ion-injection surface of the silicon substrate and the surface of a sapphire substrate ( 4 ) to one another directly or with an insulating film ( 2 ) interposed therebetween; and then obtaining a hybrid substrate ( 8 ) having a silicon thin-film (semiconductor layer; 6 ) on the sapphire substrate ( 4 ), by detaching the silicon substrate ( 1 ) in the ion-injection region ( 3 ). This method is characterized in that the adhering to the silicon substrate ( 1 ) occurs after the sapphire substrate ( 4 ) is heat-treated in advance in a reducing atmosphere.

First claim

The invention claimed is:

1. A hybrid substrate comprising a semiconductor layer on a support substrate via an insulating film, the hybrid substrate being obtained by the method comprising the steps of:
implanting ions into a surface of a semiconductor substrate to form an ion-implanted region;
bonding the ion-implanted surface of the semiconductor substrate to a surface of a support substrate via an insulating film; and
separating the semiconductor substrate at the ion-implanted region, thus leaving a hybrid substrate having a semiconductor layer on the support substrate,
wherein the support substrate is heat treated at a temperature of 700 to 1,100° C. in a reducing atmosphere for reducing the concentration of metal impurities at the surface of the support substrate and reducing a number of defects on the semiconductor layer of the hybrid substrate prior to the step of bonding the support substrate to the semiconductor substrate,
wherein at the surface of the support substrate, the concentration of Fe is up to 3×10 10 atoms/cm 2 and the concentration of Ni is up to 1×10 10 atoms/cm 2 , and a number of defects on the surface of the semiconductor layer, which is counted after immersing the hybrid substrate having an outer diameter of 150 mm in 50 wt % hydrogen fluoride solution, is 487 or less.

2. The hybrid substrate of claim 1 , wherein the support substrate is heat treated at a temperature of at least 900° C.

3. The hybrid substrate of claim 1 , wherein the reducing atmosphere is hydrogen or an inert gas atmosphere containing hydrogen.

4. The hybrid substrate of claim 1 , wherein the semiconductor substrate comprises a material selected from the group consisting of silicon, silicon-germanium, silicon carbide, germanium, gallium nitride, zinc oxide, and gallium arsenide.

5. The hybrid substrate claim 1 , wherein the support substrate comprises a material selected from the group consisting of silicon, silicon carbide, silicon nitride, sapphire, diamond, aluminum nitride, gallium nitride, zinc oxide, quartz, and borosilicate glass.

6. The hybrid substrate of claim 1 , wherein the semiconductor substrate is heat treated for at least 10 seconds and up to 12 hours.

7. The hybrid substrate of claim 1 , wherein the insulating film is a silicon oxide film, an aluminum oxide film or a silicon nitride film.

8. The hybrid substrate of claim 1 , wherein the support substrate is a sapphire substrate.

Assignees

• Shinetsu Chemical Co

Inventors

• Konishi Shigeru
• Kubota Yoshihiro

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H01L21/76254 Primary

  Electricity · mapped topic