Memory system for rapidly testing data lane integrity

Patent metadata

Field	Value
Publication number	US-9837169-B2
Application number	US-201615052366-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	Feb 24, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A memory system for a computer is provided as well as a method for integrity testing a memory interface. The memory system includes a memory controller providing a memory interface including a plurality of data lanes, wherein each of the plurality of data lanes includes a driver and a receiver, and wherein each receiver has an output. The memory system further includes an AND gate having an output and a plurality of inputs, wherein the output of each receiver is coupled to one of the plurality of inputs of the AND gate. The method includes driving a high signal pulse onto each of a plurality of data lanes of a memory interface, receiving a reflection of the high signal pulse on each of the data lanes, and determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective.

First claim

What is claimed is:

1. A method, comprising:
driving a high signal pulse onto each of a plurality of data lanes of a memory interface, wherein each of the data lanes is bidirectional, coupled to a respective input of a logical AND gate, and matched in length, and wherein the high signal pulse is simultaneously driven onto each of the plurality of data lanes;
receiving a reflection of the high signal pulse on each of the data lanes; and
determining, by using the AND logic gate, whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective.

2. The method of claim 1 , wherein determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective, includes determining that none of the data lanes is defective in response to receiving the reflections at the same time.

3. The method of claim 2 , wherein each of the data lanes includes a driver and a receiver, and wherein each driver has an output that drives the high signal pulse onto a corresponding data lane and each receiver has an input that receives the reflection of the high signal pulse on the corresponding data lane.

4. The method of claim 3 , wherein each input of the logical AND gate receives an output from a respective receiver of a respective data lane, and the logical AND outputs a signal that indicates whether any one or more of the date lanes is defective.

5. The method of claim 3 , wherein the driver generates the high signal pulse by applying a high signal to an input of the driver and then enabling and disabling the driver while the high signal is being input to the driver.

6. The method of claim 5 , wherein the driver is enabled for a single clock cycle before being disabled.

7. The method of claim 5 , further comprising:
after the driver has generated the high signal pulse, enabling the receiver to receive the reflection.

8. The method of claim 1 , wherein determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective, includes determining that one or more of the data lanes is defective in response to receiving at least one of the reflections at a different time than the other reflections.

9. The method of claim 8 , further comprising:
in response to determining that one or more of the data lanes is defective, identifying the one or more of the data lanes that is defective.

10. The method of claim 1 , further comprising:
training each of the data lanes in response to determining that none of the data lanes are defective.

11. The method of claim 1 , further comprising:
preventing the training of any of the data lanes in response to determining that one or more of the data lanes are defective.

12. A memory system for a computer, comprising:
a memory controller providing a memory interface including a plurality of data lanes, wherein each of the plurality of data lanes includes a driver and a receiver, and wherein each receiver has an output; and
an AND gate having an output and a plurality of inputs, wherein the output of each receiver is coupled to a respective one of the plurality of inputs of the AND gate, and wherein the output of the AND gate provides either a positive signal indicating that none of the data lanes of the memory interface is defective or a negative signal indicating that one or more of the data lanes of the memory interface is defective.

13. The memory system of claim 12 , further comprising:
a plurality of memory modules, wherein each memory module is coupled to the plurality of data lanes.

14. The memory system of claim 12 , wherein the memory controller provides a second memory interface including a second plurality of data lanes, and wherein each of the second plurality of data lanes includes a driver and a receiver, the memory system further comprising:
a second AND gate having an output and a plurality of inputs, wherein the output of each receiver in the second plurality of data lanes is coupled to one of the plurality of inputs of the second AND gate.

15. The memory system of claim 14 , wherein the output of the second AND gate provides either a positive signal indicating that none of the data lanes of the second memory interface is defective or a negative signal indicating that one or more of the data lanes of the second memory interface is defective.

16. The memory system of claim 12 , wherein each driver of the memory interface has an enable input coupled to a single driver enable signal line of the memory interface, and wherein each receiver of the memory interface has an enable input coupled to a single receiver enable signal line of the memory interface.

17. The memory system of claim 12 , wherein each of the data lanes are bidirectional and matched in length.

18. The memory system of claim 17 , wherein the high signal pulse is simultaneously driven onto each of the plurality of data lanes.

Assignees

• Lenovo Entpr Solutions Singapore Pte Ltd

Inventors

• Diokno Robert
• Kangas Paul D
• Weber Matthew
• Wiwel Timothy M

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C29/025

  in signal lines · CPC title

• G01R31/02

  Physics · mapped topic