Display panel

Patent metadata

Field	Value
Publication number	US-9837038-B2
Application number	US-201514848345-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Feb 5, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A display panel uses demultiplexers to reduce numbers of data lines, and divides the data lines into groups being coupled to the demultiplexers respectively. The demultiplexers are disposed along an edge of the display region and compliant to the outline of the display panel, so as to save the layout space. In addition, the layout of control lines of the demultiplexers can be configured to more effectively utilize the layout space in the layout region. Furthermore, the aforementioned layout helps reduce the length of the conductive lines, and improves the transmission of signals in the conductive lines.

First claim

What is claimed is:

1. A display panel, having a display region, a layout region, and an external circuit region, wherein the external circuit region is located at an edge of the display panel, the layout region is located between the display region and the external circuit region, and the display panel comprises:
a plurality of pixel structures, disposed in the display region;
a plurality of demultiplexers, disposed in the layout region, wherein the demultiplexers are arranged along an edge of the display region, and at least two of the demultiplexers are not located on the same horizontal axis;
a plurality of first data lines, extending from the external circuit region to the layout region and respectively coupled to the demultiplexers;
a plurality of second data lines, vertical to the horizontal axis and divided into a plurality of groups, wherein at least two second data lines in each of the groups are coupled between the corresponding demultiplexer and the corresponding pixel structures, and each of the demultiplexers receives a first data signal from the corresponding first data line, multiplexes the first data signal into at least two second data signals, and respectively transmits the at least two data signals to the at least two second data lines;
a plurality of control lines, extending from the external circuit region to the layout region and respectively coupled to the demultiplexers, wherein the control lines comprise:
a plurality of connecting line segments, located in the layout region, wherein the connecting line segments are divided into a plurality of groups, and at least two connecting line segments in each of the groups are coupled to the corresponding demultiplexer; and
a plurality of bus line segments, extending from the external circuit region to the layout region and coupled to the corresponding connecting line segments;

a plurality of gate drivers, disposed in the layout region;
a plurality of first scan lines, extending from the external circuit region to the layout region and respectively coupled to the gate drivers; and
a plurality of second scan lines, divided into a plurality of groups, wherein at least two second scan lines in each of the groups are coupled between the corresponding gate driver and the corresponding pixel structures, and a portion of each of the plurality of bus line segments and a portion of each of the plurality of first scan lines conform to the edge of the display region.

2. The display panel as claimed in claim 1 , comprising:
a first circuit layer, comprising the first data lines, the second data lines, the first scan lines, and the bus line segments;
a second circuit layer, alternately stacked with the first circuit layer, wherein the second circuit layer comprises the second scan lines and the connecting line segments; and
an insulating layer, located between the first circuit layer and the second circuit layer, such that the first circuit layer is insulated from the second circuit layer.

3. The display panel as claimed in claim 1 , wherein at least two of the bus line segments are arranged to be side by side and parallel to the first scan lines.

4. The display panel as claimed in claim 1 , wherein the edge of the display region is curved and the portion of each of the plurality of bus line segments and the portion of each of the plurality of first scan lines are parallel to the edge of the display region.

5. The display panel as claimed in claim 1 , wherein the display region is circular, and each of the bus line segments is an arc line parallel to the edge of the display region.

6. The display panel as claimed in claim 1 , wherein the edge of the display region is curved, and each of the first scan lines is a curved line parallel to the edge of the display region.

7. The display panel as claimed in claim 1 , wherein the display region is circular, and each of the first scan lines is an arc line parallel to the edge of the display region.

8. The display panel as claimed in claim 1 , wherein each of the control lines comprises:
a plurality of first line segments, located in the layout area, wherein the first line segments are coupled to and cross the corresponding demultiplexers respectively; and
a plurality of second line segments, located in the layout region, wherein the first line segments and the second line segments are arranged alternately, and the first and second line segments are coupled to each other through their head or tail portions.

9. The display panel as claimed in claim 8 , comprising:
a first circuit layer, comprising the first data lines, the second data lines, the first scan lines, and the second line segments;
a second circuit layer, alternately stacked with the first circuit layer, wherein the second circuit layer comprises the second scan lines and the first line segments; and
an insulating layer, located between the first circuit layer and the second circuit layer, such that the first circuit layer is insulated from the second circuit layer.

Assignees

• Au Optronics Corp

Inventors

• Lee Chia-Hwa

Classifications

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title