System and method for bit error rate monitoring

Patent metadata

Field	Value
Publication number	US-9836341-B2
Application number	US-201414307029-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Mar 16, 2011
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

In an embodiment, a method of determining whether to trigger an event based on data blocks having status data includes electronically receiving the data blocks over a channel, performing a data integrity check on the data blocks to determine whether a particular data block has a transmission fault, calculating a received error metric based on performing the data integrity check, and disabling an event trigger if the received error metric crosses a first error threshold.

First claim

What is claimed is:

1. A system comprising:
a control unit configured to be coupled to a sensor, the control unit configured to:
electronically receive data blocks from the sensor;
perform a data integrity check on the data blocks to determine whether a particular data block has a transmission fault;
calculate a received error metric based on performing the data integrity check, the received error metric comprising a received error rate; and
disable an event trigger if the received error metric crosses a first error threshold, wherein the control unit is further configured to enable the event trigger after the event trigger has been disabled if the received error metric is less than a second error threshold, wherein the second error threshold is less than the first error threshold.

2. The control unit of claim 1 , wherein the control unit is further configured to trigger an event if the data blocks have status data that meets an event trigger criterion, and if the event trigger is not disabled.

3. The control unit of claim 2 , wherein:
the status data represents an output of the sensor; and
triggering the event comprises generating an air bag firing signal.

4. The control unit of claim 1 , wherein the data blocks comprise cyclic redundancy check (CRC) fields, and wherein performing the data integrity check comprises performing a CRC check.

5. The control unit of claim 1 , wherein calculating the received error metric comprises counting transmission faults within a defined time window, and wherein the received error metric comprises a number of transmission faults within a specified time window.

6. The control unit of claim 1 , wherein calculating the received error metric comprises determining a time between two transmission faults.

7. The control unit of claim 1 , wherein calculating the received error metric comprises filtering occurrences of transmission faults with respect to time.

8. The control unit of claim 1 , wherein the control unit is configured to receive the data blocks over a plurality of channels configured to be coupled to a plurality of sensors.

9. The control unit of claim 1 , wherein the control unit is further configured to generate a control signal to increase a data rate of the data blocks after disabling the event trigger.

10. A system for triggering an event, the system comprising:
an input interface configured to receive data blocks from a sensor;
a data integrity check circuit configured to determine if the data blocks contain data errors;
an error monitor configured to determine a received error metric based on data errors detected by the data integrity check circuit; and
an event triggering circuit configured to:
disable an event trigger if the received error metric is greater than a first error threshold,
enable the event trigger if the received error metric is below a second error threshold, wherein the second error threshold is less than the first error threshold, and
trigger the event if the data blocks meet event triggering criteria, and if the event trigger is enabled.

11. The system of claim 10 , wherein the event comprises firing an airbag in an airbag system.

12. The system of claim 10 , wherein the data integrity check circuit performs a cyclic redundancy check (CRC).

13. The system of claim 10 , wherein the error monitor comprises a counter that captures a time between two detected data errors.

14. The system of claim 10 , wherein the error monitor comprises an error counter that monitors a number of detected data errors within a defined time window.

15. A safety system comprising:
an interface circuit configured to be coupled to a plurality of sensors,
an internal data bus coupled to the interface circuit,
a trigger circuit coupled to the internal data bus and configured to be coupled to a safety device, wherein the trigger circuit is configured to detect an event based on sensor data received on the internal data bus and to trigger the safety device, and
a data integrity circuit coupled to the internal data bus and the trigger circuit, wherein the data integrity circuit is configured to calculate an error metric corresponding to the sensor data received on the internal data bus and disable the trigger circuit if the error metric is above a first error threshold.

16. The safety system of claim 15 , further comprising the plurality of sensors and the safety device, wherein the safety device comprises an air bag and triggering the safety device comprises firing the air bag.

17. The safety system of claim 15 , further comprising an internal sensor coupled to the internal data bus and configured to sense acceleration.

18. The safety system of claim 15 , wherein the data integrity circuit comprises a safety integrity check circuit and a safing drive circuit configured to enable or disable the trigger circuit based on a control signal from the safety integrity check circuit.

19. The safety system of claim 18 , wherein the error metric is calculated by:
performing a data integrity check on data blocks in the sensor data received over the internal data bus in order to determine whether a particular data block has a transmission fault; and
calculating the error metric based on performing the data integrity check.

Assignees

• Infineon Technologies Ag

Inventors

• Hammerschmidt Dirk
• Dittfeld Timo

Classifications

• H04L1/201

  Frame classification, e.g. bad, good or erased (frame indication per se H04L1/0082) · CPC title

• H04L1/203

  Details of error rate determination, e.g. BER, FER or WER · CPC title

• H04L1/0061 Primary

  Error detection codes · CPC title

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title