Low power distributed memory network

Patent metadata

Field	Value
Publication number	US-9836235-B2
Application number	US-201514700755-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	May 7, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A digital signal processing (DSP) system includes an analog to digital converter, program random access memory (PRAM), N switching devices, and a control module. The analog to digital converter is configured to convert samples of an analog signal into digital samples. The PRAM includes: N PRAM blocks, where N is an integer greater than one; and code for M digital signal processing functions stored in the N PRAM blocks, where M is an integer greater than one. The N switching devices are configured to connect and disconnect the N PRAM blocks, respectively, to and from a power source. The control module is configured to: control the N switching devices; and execute selected ones of the M digital signal processing functions on the digital samples to produce an output.

First claim

What is claimed is:

1. A digital signal processing (DSP) system comprising:
an analog to digital converter configured to convert samples of an analog signal into digital samples;
program random access memory (PRAM) including:
N PRAM blocks, wherein N is an integer greater than one; and
code for M digital signal processing functions stored in the N PRAM blocks, wherein M is an integer greater than one, and
wherein last lines of the code for each of the M digital signal processing functions includes: (i) an instruction to determine a next one of the M digital signal processing functions to be executed; and (ii) an indicator of a wake up period of one of the N PRAM blocks where the next one of the M digital signal processing functions is stored;

N switching devices configured to connect and disconnect the N PRAM blocks, respectively, to and from a power source; and
a control module configured to:
control the N switching devices; and
read and execute, from the PRAM, selected ones of the M digital signal processing functions on the digital samples to produce an output,
wherein the control module is configured to:
selectively actuate a first one of the N switching devices to connect a first one of the N PRAM blocks to the power source;
execute a first portion of the code for a first one of the M digital signal processing functions stored in the first one of the N PRAM blocks;
in response to executing the last line of the code for the first one of the M digital signal processing functions: (i) determine a second one of the M digital signal processing functions that is to be executed next after the first one of the M digital signal processing functions; and (ii) determine a wake up period of a second one of the N PRAM blocks where the second one of the M digital signal processing functions is stored;
actuate the first one of the N switching devices to disconnect the first one of the N PRAM blocks from the power source after the execution of the last line of code for the first one of the M digital signal processing functions;
based on the determination that the second one of the M digital signal processing functions is to be executed next after the first one of the M digital signal processing functions, selectively actuate a second one of the N switching devices to connect the second one of the N PRAM blocks to the power source; and
in response to passing of the wake up period of the second one of the N PRAM blocks after the actuation of the second one of the N switching devices to connect the second one of the N PRAM blocks to the power source, begin executing a second portion of the code for the second one of the M digital signal processing functions.

2. The DSP system of claim 1 , further comprising a register storing M indicators of whether or not to execute the M digital signal processing functions, respectively,
wherein the control module is configured to select and execute the selected ones of the M digital signal processing functions based on the M indicators stored in the register.

3. The DSP system of claim 2 , wherein, when one of the M indicators in the register indicates that execution of a third of the M digital signal processing functions is disabled, the control module is configured to disconnect a third one of the N PRAM blocks storing the third one of the M digital signal processing functions from the power source during a period between a beginning of a digital sample and an end of the digital sample.

4. The DSP system of claim 1 , further comprising a counter configured to increment a counter value based on a clock signal,
wherein the control module is configured to execute lines of the code based on the counter value.

5. The DSP system of claim 4 , wherein the control module is configured to selectively set the counter value to a line number of the code corresponding to a first line of the code for the second one of the M digital signal processing functions a the wake up period after the actuation of the second one of the N switching devices to connect the second one of the N PRAM blocks to the power source.

6. The DSP system of claim 4 , wherein the control module is configured to maintain the counter value for the wake up period after the actuation of the second one of the N switching devices to connect the second one of the N PRAM blocks to the power source.

7. The DSP system of claim 4 , wherein the control module is configured to reset the counter value each time when a digital sample is received.

8. A method for reducing power consumption of a digital signal processing (DSP) system, the method comprising:
converting samples of an analog signal into digital samples;
selectively connecting and disconnecting N program random access memory (PRAM) blocks to and from a power source using N switching devices, respectively,
wherein N is an integer greater than one,
wherein code for M digital signal processing functions is stored in the N PRAM blocks, and
wherein M is an integer greater than one, and
wherein last lines of the code for each of the M digital signal processing functions includes: (i) an instruction to determine a next one of the M digital signal processing functions to be executed; and (ii) an indicator of a wake up period of one of the N PRAM blocks where the next one of the M digital signal processing functions is stored;
controlling the N switching devices; and
reading and executing, from the PRAM, selected ones of the M digital signal processing functions on the digital samples to produce an output,
wherein the controlling and the reading and executing include:
selectively actuating a first one of the N switching devices to connect a first one of the M digital signal processing functions to the power source;
executing a first portion of the code for a first one of the M digital signal processing functions stored in the first one of the N PRAM blocks;
in response to executing the last line of the code for the first one of the N PRAM blocks: (i) determining a second one of the M digital signal processing functions that is to be executed next after the first one of the M digital signal processing functions; and (ii) determining a wake up period of a second one of the N PRAM blocks where the second one of the M digital signal processing functions is stored;
actuating the first one of the N switching devices to disconnect the first one of the N PRAM blocks from the power source after the execution of the last line of the code for the first one of the M digital signal processing functions;
based on the determination that the second one of the M digital signal processing functions is to be executed next after the first one of the M digital signal processing functions, selectively actuating a second one of the N switching devices to connect the second one of the N PRAM blocks to the power source; and
in response to passing of the wake up period of the second one of the N PRAM blocks after the actuation of the second one of the N switching devices to connect the second one of the N PRAM blocks to the power source, beginning to execute a second portion of the code for the second one of the M digital signal processing functions.

9. The method of claim 8 further comprising:
storing in a register M indicators of whether or not to execute the M digital signal processing functions, respectively; and
selecting and executing the selected ones of the M digital signal processing functions based on the M indicators stored in the register.

10. The method of claim 9 , further comprising, when one of the M indicators in the register indicates that execution of a third one of the M digital signal processing functions is disabled, disconnecting a third one of the N PRAM

Assignees

• Marvell World Trade Ltd

Inventors

• Jain Kapil
• Pan Wenzong
• Wang Cai

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F1/3212 Primary

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title