Configurable high speed FPGA scan mechanism controller

Patent metadata

Field	Value
Publication number	US-9836221-B1
Application number	US-201514937715-A
Country	US
Kind code	B1
Filing date	Nov 10, 2015
Priority date	Nov 10, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Control systems and methods are provided. The systems and methods include a field programmable gate array (FPGA) in which a plurality of functional processing units (FPUs) are formed, and one or memories having a plurality of memory locations. An input signal is received from a sensor and is processed in at least some of the FPUs. The FPUs can be reused one or more times during the processing of a single input signal. The system can also receive a control signal as an additional input. In response to the inputs, an output signal is generated. The output signal can be used to control an actuator. In accordance with further embodiments, the operation of the FPUs can be reconfigured by storing different operating parameter values in memory.

First claim

What is claimed is:

1. A method for controlling a physical system, comprising:
receiving an input signal at an input port, wherein the input signal represents a first system parameter;
storing the input signal at a first address in a memory;
providing the input signal from the first address in the memory as an operand to a first functional block of a field programmable gate array (FPGA), wherein the first functional block generates at least a first intermediate output value, wherein the first functional block is determined by a state machine, and wherein the input signal is provided from the first address in the memory to the first functional block over a first programmable interconnect;
storing the first intermediate output value in a second address in the memory, wherein the second address in the memory is determined by the state machine, and wherein the first intermediate output value is provided from the first functional block to the second address in the memory over a second programmable interconnect;
providing the first intermediate output value from the second address in the memory as an operand to a second functional block of the FPGA, wherein the second functional block generates at least a second intermediate output value, wherein the second functional block is determined by the state machine, and wherein the first intermediate output is provided from the second address in the memory to the second functional block over a third programmable interconnect;
storing the second intermediate output value in a third address in the memory, wherein the third address in the memory is determined by the state machine, and wherein the second intermediate output value is provided from the second functional block to the third address in the memory over a fourth programmable interconnect; and
providing a final output value from the memory to an output port.

2. The method of claim 1 , further comprising:
providing the second intermediate output value from the third address in the memory as an operand to the first functional block of the FPGA, wherein the first functional block generates a third intermediate output value, and wherein operations of the functional blocks are performed in a timed sequence.

3. The method of claim 2 , wherein the generation of the first intermediate output value by the first functional block of the FPGA and the generation of the third intermediate output value are performed at different times.

4. The method of claim 3 , further comprising:
providing a first parameter value from the memory to the first functional block of the FPGA;
providing a second parameter value from the memory to the first functional block of the FPGA, wherein at least the first parameter value is applied by the first functional block of the FPGA in generating the first intermediate output value.

5. The method of claim 4 , wherein the second parameter value is applied by the first functional block of the FPGA in generating the third intermediate value.

6. The method of claim 1 , wherein at least the first functional block uses a math processing parameter to perform an operation on an operand, and wherein the math processing parameter is stored in the memory, the method further comprising:
providing a first parameter value from the memory to the first functional block of the FPGA, wherein the first parameter value is the math processing parameter.

7. The method of claim 6 , wherein the first parameter value is applied by the first functional block of the FPGA in generating the first intermediate output value.

8. The method of claim 1 , wherein the first functional block of the FPGA is a floating point math processing unit.

9. The method of claim 8 , wherein the floating point math processing unit performs at least one of the following operations: addition, subtraction, multiplication, division, and absolute value generation.

10. The method of claim 1 , further comprising:
receiving an analog input signal at an input interface;
filtering the analog input signal to obtain a filtered input signal;
digitizing the filtered input signal to obtain a digital input signal;
converting the digital input signal to a floating point formatted value, wherein the floating point formatted value is the input signal stored in the first address in the memory.

11. The method of claim 10 , wherein the analog input signal is received from a sensor, and wherein the output signal is provided from the output port to an actuator.

12. A system, comprising:
a sensor, wherein the sensor is operable to provide an analog output signal;
an input interface, wherein the input interface is operable to receive the analog output signal from the sensor as an input signal and to convert the analog output signal to a digital input signal;
a field programmable gate array (FPGA), wherein a plurality of functional processing units (FPUs) are defined in the FPGA;
memory, wherein the memory includes a plurality of memory locations, and wherein each of the plurality of memory locations is associated with an address;
a state machine;
a plurality of programmable interconnects, wherein a plurality of communication paths are formed using the programmable interconnects, based on operation of the state machine;
and
an actuator, wherein the actuator is connected to an output of the FPGA by an output signal line,
wherein a first memory location having a first memory address receives the digital input signal from the input interface during a first clock cycle,
wherein the first memory location is operable to store the digital input signal received from the input interface,
wherein the first memory location is connected to a first FPU by a first communication path during at least a second clock cycle,
wherein the first communication path is operable to provide the digital input signal to the first FPU during the second clock cycle,
wherein the first FPU is operable to generate a first intermediate value using the digital input signal,
wherein a second memory location having a second memory address is connected to the first FPU by a second communication path during at least a third clock cycle,
wherein the second communication path is operable to provide the first intermediate value to the second memory location during the third clock cycle,
wherein the second memory location is operable to store the first intermediate value,
wherein a second FPU is connected to the second memory location by a third communication path during at least a fourth clock cycle,
wherein the third communication path is operable to provide the first intermediate value to the second FPU during the fourth clock cycle,
wherein the second FPU is operable to generate one of a second intermediate value and a final output value,
wherein a third memory location having a third memory address is connected to the second FPU by a fourth communication path during at least a fifth clock cycle, and
wherein the fourth communication path is operable to provide the one of the second intermediate value and the final output value to the third memory location during the fifth clock cycle.

13. The system of claim 12 , wherein the memory is a dual-port memory included as part of the FPGA.

14. The system of claim 13 , wherein the sensor is a position sensor, and wherein the actuator is a motor.

15. The system of claim 12 , wherein a fourth memory location is connected to a parameter input of the first FPU during the second clock cycle.

16. The system of claim 12 , wherein the second FPU is operable to generate a second intermediate value, wherein the third memory lo

Assignees

• Ball Aerospace & Tech Corp

Inventors

• Edfors Scott E

Classifications

• G05B19/042 Primary

  using digital processors (G05B19/05 takes precedence) · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/064

  Management of blocks · CPC title