Array substrate and display device

Patent metadata

Field	Value
Publication number	US-9836155-B2
Application number	US-201514418189-A
Country	US
Kind code	B2
Filing date	Jan 16, 2015
Priority date	Dec 19, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Disclosed are an array substrate and a display device which belong to the technical field of displays, and solve the technical problem that, in the existing in-cell technology, the manufacturing process of array substrates is too complex. The array substrate comprises a plurality of pixel units each having a thin film transistor, a plurality of common electrodes, and a plurality of address lines. The address lines each are formed by connecting a first metal wire and a second metal wire, the first metal wire being located at a same layer as a gate of the thin film transistor, and the second metal wire being located at a same layer as a source and a drain of the thin film transistor.

First claim

The invention claimed is:

1. An array substrate, comprising:
a plurality of pixel units each having a thin film transistor, and
a plurality of common electrodes and a plurality of address lines for transmitting touch signals, each of the address lines being connected to a corresponding common electrode,
wherein the common electrodes each are used to provide a common voltage for a corresponding pixel unit, and generate a touch signal, and
the address lines each are formed by connecting a first metal wire and a second metal wire, the first metal wire being located at a same layer as a gate of the thin film transistor, and the second metal wire being located at a same layer as a source and a drain of the thin film transistor.

2. The array substrate according to claim 1 , further comprising a plurality of scan lines and a plurality of data lines, wherein the first metal wire is located right below the data lines.

3. The array substrate according to claim 1 , wherein the first metal wire and the second metal wire are connected to each other through a connecting piece, and are connected to the connecting piece through a via hole, respectively.

4. The array substrate according to claim 3 , wherein the connecting piece and a low temperature poly-silicon in the thin film transistor are located at a same layer.

5. The array substrate according to claim 4 , wherein the thin film transistor is in the form of a top-gate thin film transistor.

6. The array substrate according to claim 5 , wherein a light shielding layer is provided under the low temperature poly-silicon in the thin film transistor and the connecting piece.

7. The array substrate according to claim 1 , wherein the first metal wire and the second metal wire are connected to each other directly through a via hole.

8. The array substrate according to claim 1 , wherein one common electrode corresponds to one or more of the pixel units.

9. A display device, comprising:
a color filter substrate; and
an array substrate, wherein the array substrate includes:
a plurality of pixel units each having a thin film transistor, and
a plurality of common electrodes and a plurality of address lines for transmitting touch signals, each of the address lines being connected to a corresponding common electrode,
wherein the common electrodes each are used to provide a common voltage for a corresponding pixel unit, and generate a touch signal, and
the address lines each are formed by connecting a first metal wire and a second metal wire, the first metal wire being located at a same layer as a gate of the thin film transistor, and the second metal wire being located at a same layer as a source and a drain of the thin film transistor.

10. The display device according to claim 9 , further comprising a plurality of scan lines and a plurality of data lines, wherein the first metal wire is located right below the data lines.

11. The display device according to claim 9 , wherein the first metal wire and the second metal wire are connected to each other through a connecting piece, and are connected to the connecting piece through a via hole, respectively.

12. The display device according to claim 11 , wherein the connecting piece and a low temperature poly-silicon in the thin film transistor are located at a same layer.

13. The display device according to claim 12 , wherein the thin film transistor is in the form of a top-gate thin film transistor.

14. The display device according to claim 13 , wherein a light shielding layer is provided under the low temperature poly-silicon in the thin film transistor and the connecting piece.

15. The display device according to claim 9 , wherein the first metal wire and the second metal wire are connected to each other directly through a via hole.

16. The display device according to claim 9 , wherein one common electrode corresponds to one or more of the pixel units.

17. The display device according to claim 9 , wherein the display device is a fringe field switching liquid crystal display device.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelectrics Tech Co Ltd

Inventors

• Ming Xing
• Shen Zhiyuan

Classifications

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G06F2203/04107

  Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title