Driver and capacitive load integration

Patent metadata

Field	Value
Publication number	US-9835880-B2
Application number	US-201615231939-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Jun 8, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A circuit that may include a circuit network and a transmission line coupled to the circuit network. The circuit network may include an electro-optic modulator and various inductors. The electro-optic modulator may be a capacitive load having a predetermined capacitance. The circuit may further include a resistor coupled to the circuit network. The resistor may have a resistance value configured to produce a first impedance with the circuit network. The first impedance may be configured to match substantially with a second impedance in the transmission line. The circuit may further include an electric driver couple to the transmission line. The electric driver may be configured for transmitting a driving voltage to the electro-optic modulator. The driving voltage may be configured to generate a predetermined voltage swing across the electro-optic modulator.

First claim

What is claimed is:

1. A circuit, comprising:
a circuit network comprising a capacitive load and a plurality of inductors, wherein the capacitive load has a predetermined capacitance;
a first transmission line coupled to the circuit network;
a resistor coupled to the circuit network, the resistor having a resistance value configured to produce a first impedance with the circuit network, and wherein the first impedance is configured to match substantially with a second impedance of the first transmission line; and
an electric driver coupled to the first transmission line,
wherein the electric driver is configured for transmitting a driving voltage to the capacitive load, and
wherein the driving voltage is configured to generate a predetermined voltage swing across the capacitive load.

2. The circuit of claim 1 , wherein the plurality of inductors within the circuit network have no mutual coupling.

3. The circuit of claim 1 , wherein the circuit network comprises a bridged-T network.

4. The circuit of claim 1 ,
wherein the capacitive load is a mechanical transducer, and
wherein the voltage swing corresponds to a difference between a first power output of the mechanical transducer and a second power output of the mechanical transducer.

5. The circuit of claim 1 , wherein the capacitive load is a microelectromechanical system (MEMS) device.

6. The circuit of claim 1 , further comprising:
wherein the electric driver and the capacitive load are separated by a predetermined distance within an assembly,
wherein the first transmission line spans at least a portion of the predetermined distance, and
wherein a material medium of the first transmission line is configured with a predetermined impedance based on the at least the portion of the predetermined distance.

7. The circuit of claim 1 ,
wherein the first transmission line is configured to produce a predetermined impedance mismatch with the bridged-T network, and
wherein the predetermined impedance mismatch is configured to generate a predetermined electrical reflection from the bridged-T network to the electric driver through the first transmission line.

8. The circuit of claim 1 , wherein the predetermined capacitance is based on a predetermined transducer efficiency.

9. The circuit of claim 1 , wherein the first transmission line is a tapered transmission line.

10. The circuit of claim 1 , wherein the first transmission line is a microstrip.

11. The circuit of claim 1 , further comprising:
a second transmission line coupled to the capacitive load; and
a terminating resistor coupled to the second transmission line.

12. The circuit of claim 1 , wherein the predetermined capacitance corresponds to a gap between electrodes in the capacitive load.

13. A circuit, comprising:
a capacitive load configured with a first predetermined capacitance;
an electric driver, wherein the electric driver is configured for transmitting a driving voltage to the capacitive load, and wherein the driving voltage is configured to generate a predetermined voltage swing across the capacitive load;
a first inductor-and-capacitor (LC) ladder network compensation circuitry; and
a second LC ladder network compensation circuitry, wherein the first and second LC ladder network compensation circuitries are configured for matching the electric driver with the capacitive load.

14. The circuit of claim 13 ,
wherein the first LC ladder network circuitry comprises a second predetermined capacitance configured using an open-circuited stub.

15. The circuit of claim 13 , wherein the first LC ladder network circuitry comprises a predetermined inductance configured using a short-circuited stub.

16. The circuit of claim 13 , wherein the predetermined capacitance is configured based on a predetermined voltage eye opening across the capacitive load.

17. The circuit of claim 13 ,
wherein the capacitive load is a mechanical transducer, and
wherein the voltage swing corresponds to a difference between a first power output of the mechanical transducer and a second power output of the mechanical transducer.

18. The circuit of claim 13 , wherein the capacitive load is a microelectromechanical system (MEMS) device.

Assignees

• Pelekhaty Vladimir
• Frankel Michael Y
• Ciena Corp

Inventors

• Pelekhaty Vladimir
• Frankel Michael Y

Classifications

• H01L41/09

  Electricity · mapped topic

• G02F1/0121 Primary

  Operation of devices; Circuit arrangements, not otherwise provided for in this subclass · CPC title

• H10N30/20

  with electrical input and mechanical output, e.g. functioning as actuators or vibrators · CPC title