Output current monitoring circuit

Patent metadata

Field	Value
Publication number	US-9835655-B2
Application number	US-201414308789-A
Country	US
Kind code	B2
Filing date	Jun 19, 2014
Priority date	Jun 6, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A current monitoring circuit capable of being integrated onto an integrated circuit chip with the current source to be monitored, wherein the monitored current is digitized to be transmitted within and external to the host integrated circuit chip. The current monitoring circuit was originally conceived to monitor output current of a buck switching regulator but can be used in other applications. A replica transistor is drain connected to a replicated transistor, wherein an operational transconductor controls the replica transistor to produce the same current that flows in the replicated transistor and connects a copy of the current of the replicated transistor current to an integrating type ADC.

First claim

What is claimed is:

1. A current monitor, comprising:
a) a transistor, wherein a current flowing through this transistor is to be monitored and wherein this transistor is replicated by a replica transistor;
b) said replica transistor, which is a scaled down version of the replicated transistor, wherein a drain of the replica transistor is connected to a drain of the replicated transistor;
c) a sample and hold circuit, comprising a sampling switch, a resistor and a capacitor, is connected to a first input of an operational transconductor, wherein the sample and hold circuit is configured to sample and hold input signals from a source of the replica transistor during the time that the replicated transistor is powered on and hold the value of the input signals during the time that the replicated transistor is switched off, wherein a first terminal of the sampling switch is connected to a source of the replica transistor, a second terminal of the sampling switch is connected to a first terminal of the resistor, a second terminal of the resistor is connected to a first terminal of the capacitor and to the first input of the operational transconductor and a second terminal of the capacitor is connected to ground;
d) said operational transconductor (OTA) having two inputs and two current outputs, wherein the first input of said OTA is connected via the sample and hold circuit to a source of the replica transistor and wherein a second input of said OTA is connected to a source of the replicated transistor, wherein each output of the OTA is coupled to one of two current sources, wherein the first current source is configured to drive a feedback loop to the source of the replica transistor and the second current source is configured to provide an analog value of the replica transistor current to a current mode integrating analog to digital converter for conversion into a digital current value;
e) said current mode integrating analog to digital converter (ADC) configured to provide a digital output of the current monitor; and
f) wherein said replicated transistor is configured to produce the current to be monitored, wherein said OTA is configured to control a source current of the replica transistor to be of a proportional current value as a source current of the replicated transistor while said OTA is configured to produce an output current equivalent to the source current of the replicated transistors.

2. The current monitor of claim 1 , wherein said replicated transistor plus said replica transistor are capable of producing a total current flowing through an inductor of a switching regulator during an on state of an NMOS driver transistor.

3. The current monitor of claim 2 , wherein the replica transistor is capable of being controlled by the OTA to produce a voltage drop across the replica transistor which is equivalent to the voltage drop across the replicated transistor.

4. The current monitor of claim 1 , wherein said replica transistor is capable of being sized to produce a reduced current proportional to the replicated transistor at a same drain to source voltage.

5. The current monitor of claim 1 , wherein the replica transistor is a device constructed on a same integrated circuit as the replicated transistor and comprising the same characteristics as the replicated transistor.

6. The current monitor of claim 1 , wherein the OTA is capable of controlling the source voltage of the replica transistor to a virtual ground voltage to produce the same value of current as the replicated transistor.

7. The current monitor of claim 6 , wherein the OTA is capable of producing a proportionally reduced current from the replica transistor, wherein the replica transistor is a scaled down replica transistor by controlling the source voltage of the replica transistor to the virtual ground voltage.

8. The current monitor of claim 1 , wherein the current mode integrating type ADC is a continuous time-sigma delta ADC (CT-SD ADC).

9. The current monitor of claim 1 , wherein the current mode integrating type ADC is a dual slope integral ADC.

10. The current monitor of claim 1 , wherein a sample switch, a resistor and a capacitor are configured to sample information of the average current flowing through the replicated transistor while the replicated transistor is ON and to hold the current information during the time the replicated transistor is OFF, wherein the sample switch and the resistor are connected in series with a first input of the OTA and the capacitor is connected between the first input of the OTA and ground, wherein the second input of the OTA is connected to ground and to the source of the replicated transistor and wherein the sample switch is only ON while the replicated transistor is ON.

11. The current monitor of claim 1 , wherein the replicated transistor and the replica transistor are both NMOS transistors.

12. The current monitor of claim 1 , wherein the replicated transistor and the replica transistor are both PMOS transistors.

13. A method of monitoring output current of a switching regulator, comprising;
a) forming a scaled down replica transistor wherein a drain of the replica transistor is coupled to a replicated output transistor of a switching regulator;
b) sampling and holding output signals of the replica transistor during the time the replicated transistor is ON, holding the value of the signals during the time the replicated transistor is OFF and provide then the signals to an input of an operational transconductor;
c) controlling said replica transistor with the operational transconductor (OTA) to produce a proportional current value in said replica transistor as in the replicated transistor; and
d) producing an output current from the OTA and coupling the output current to a current mode continuous time integrating analog to digital converter (ADC) for digital readout of the replicated current.

14. The method of claim 13 , wherein said switching regulator is a buck switching regulator.

15. The method of claim 13 , wherein said replica transistor is integrated on a same integrated circuit device as the replicated transistor and has a same characteristic as the replicated transistor.

16. The method of claim 13 , wherein said replica transistor and the replicated transistor are connected by drain terminals of each transistor.

17. The method of claim 13 , wherein said OTA controls the replica transistor source current to produce a proportional value of source current of the replicated transistor by controlling the source terminal voltage of the replica transistor to be at a virtual ground voltage.

18. The method of claim 13 , wherein said OTA produces two identical output currents, wherein a first output current is used for feedback and a second output current is used to connect to an ADC.

19. The method of claim 13 , wherein the current mode continuous time integrating type ADC is a continuous time-sigma delta ADC (CT-SD ADC).

20. The method of claim 13 , wherein the current mode integrating type ADC is a dual slope integral ADC.

21. The method of claim 13 , wherein the replicated transistor and the replica transistor combine to produce a total current flowing through an inductor of a switching regulator.

22. The method of claim 13 , wherein a sample switch, a resistor and a capacitor are configured to sample information of the average current flowing through the replicated transistor while the replicated transistor is ON and to hold the current information during the time

Assignees

• Dialog Semiconductor Gmbh
• Dialog Semiconductor Uk Ltd

Inventors

• Ozawa Seiichi

Classifications

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/1582

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M2001/0009

  Electricity · mapped topic

• G01R19/0092 Primary

  Measuring current only · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title