Method for manufacturing MEMS torsional electrostatic actuator

Patent metadata

Field	Value
Publication number	US-9834437-B2
Application number	US-201515327230-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Dec 2, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method for manufacturing an MEMS torsional electrostatic actuator comprises: providing a substrate, wherein the substrate comprises a first silicon layer, a buried oxide layer and a second silicon layer that are laminated sequentially; patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper electrode plate separated from a peripheral region, wherein the upper electrode plate and the peripheral region are connected by only using a cantilever beam, and forming, on the peripheral region, a recessed portion exposing the buried oxide layer; patterning the second silicon layer and exposing the buried oxide layer to form a back cavity, wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, covers 40% to 60% of the area of the region corresponding to the upper electrode plate, and is close to one end of the cantilever beam; exposing the second silicon layer, and suspending the upper electrode plate and the cantilever beam; and respectively forming an upper contact electrode and a lower contact electrode on the second silicon layer.

First claim

What is claimed is:

1. A method of manufacturing an MEMS torsional electrostatic actuator, comprising:
providing a substrate comprising a first silicon layer, a buried oxide layer, and a second silicon layer that are laminated sequentially;
patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper electrode plate spaced apart from a peripheral region, wherein the upper electrode plate is connected to the peripheral region merely via a cantilever beam, and forming a recessed portion on the peripheral region to expose the buried oxide layer simultaneously; patterning the second silicon layer and exposing the buried oxide layer to form a back cavity, wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, and the back cavity covers 40% to 60% of the area of the region corresponding to the upper electrode plate, and the back cavity is adjacent to an end of the cantilever beam;
removing the buried oxide layer that is exposed from the recessed portion to expose the second silicon layer, and removing partial buried oxide layer to suspend the upper electrode plate and the cantilever beam; and
forming an upper contact electrode and a lower contact electrode on the peripheral region and the second silicon layer exposed from the recessed portion, respectively.

2. The method according to claim 1 , wherein a resistivity of the first silicon layer and the second silicon layer range from 0.001 Ω·cm to 0.01 Ω·cm.

3. The method according to claim 1 , wherein the first silicon layer and the second silicon layer are made of monocrystalline silicon.

4. The method according to claim 1 , wherein the first silicon layer has a thickness ranging from 5 micrometers to 50 micrometers.

5. The method according to claim 1 , wherein the buried oxide layer has a thickness ranging from 0.5 micrometers to 2 micrometers.

6. The method according to claim 1 , wherein the second silicon layer has a thickness ranging from 400 micrometers to 600 micrometers.

7. The method according to claim 1 , wherein a number of the cantilever beams is two, and the back cavity is adjacent to an inner end of any one of the cantilever beams.

8. The method according to claim 1 , wherein the buried oxide layer exposed from the recessed portion is removed by using a hydrofluoric acid to expose the second silicon layer, the partial buried oxide layer is removed by using a hydrofluoric acid to suspend the upper electrode plate and the cantilever beam.

9. The method according to claim 1 , wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, and the back cavity covers 40% to 60% of the area of the region corresponding to the upper electrode plate.

10. The method according to claim 1 , wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, and the back cavity covers 50% of the area of the region corresponding to the upper electrode plate.

11. The method according to claim 1 , wherein the upper contact electrode and the lower contact electrode are formed on the peripheral region and the second silicon layer exposed from the recessed portion, respectively, by depositing a metal layer and patterning the metal layer.

Assignees

• Csmc Technologies Fab1 Co Ltd
• Csmc Tech Fabi Co Ltd

Inventors

• Jing Errong

Classifications

• B81C1/00182 Primary

  Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer · CPC title

• B81B2203/0118

  Cantilevers · CPC title

• B81B2203/0315

  Cavities · CPC title

• B81B2203/04

  Electrodes · CPC title

• B81B3/0021

  Transducers for transforming electrical into mechanical energy or vice versa (dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00) · CPC title