Embedded metallic structures in glass

US9832867B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9832867-B2
Application numberUS-201514949277-A
CountryUS
Kind codeB2
Filing dateNov 23, 2015
Priority dateNov 23, 2015
Publication dateNov 28, 2017
Grant dateNov 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A device having embedded metallic structures in a glass is provided. The device includes a first wafer, at least one conductive trace, a planarized insulation layer and a second wafer. The first wafer has at least one first wafer via that is filled with conductive material. The at least one conductive trace is formed on the first wafer. The at least one conductive trace is in contact with the at least one first wafer via that is filled with the conductive material. The planarized insulation layer is formed over the first wafer and at least one conductive trace. The planarized insulation layer further has at least one insulation layer via that provides a path to a portion of the at least one conductive trace. The second wafer is bonded to the planarized insulation layer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A device having embedded metallic structures in a glass comprising: a first wafer having at least one first wafer via filled with conductive material; at least one conductive trace formed on the first wafer, the at least one conductive trace being in contact with the at least one first wafer via filled with the conductive material; a planarized insulation layer formed over the first wafer and at least one conductive trace, the planarized insulation layer further having at least one insulation layer via that provides a path to a portion of the at least one conductive trace, at least one conductive contact layer within at least a portion of the at least one insulation layer via, the at least one conductive contact layer being in contact with the at least one conductive trace: and a second wafer fusion bonded to the planarized insulation layer, the second wafer having at least one non-filled via aligned with the at least one conductive contact layer, and at least one antennal structure in the first wafer, the antenna structure comprising a metal filled channel in the first wafer in contact with a second first wafer via filled with conductive material. 2. The device having embedded metallic structures in a glass of claim 1 , wherein the first wafer and the second wafer are made of at least one from a group including silica, borosilicate glass, sapphire and quartz. 3. The device having embedded metallic structures in a glass of claim 1 , wherein the conductive trace comprises at least one of titanium nitride, titanium, niobium, tantalum, platinum, platinum, iridium, titanium nitride alloy, titanium alloy, niobium alloy, tantalum alloy, platinum alloy, platinum alloy and iridium alloy and the conductive material that fills the first wafer via comprises at least one of copper, tungsten, copper glass composite, platinum glass composite, silver, silver filled epoxy and silver filled glass. 4. The device having embedded metallic structures in a glass of claim 1 , wherein the planarized insulation layer is at least one layer of silicon dioxide. 5. The device having embedded metallic structures in a glass of claim 1 , wherein the planarized insulation layer is made up of a plurality of sub-layers of silicon dioxide and silicon nitride. 6. The device having embedded metallic structures in a glass of claim 1 , wherein the embedded metallic structure in glass is part of a package of an implantable medical device. 7. The device having embedded metallic structures in glass of claim 1 , wherein the at least one conductive contact layer is a layer comprising titanium, titanium nitride, niobium or tantalum. 8. The device of claim 1 , wherein the second wafer has a thickness that is greater than 25 μm. 9. The device having embedded metallic structures in glass of claim 1 , wherein the at least one conductive trace is at least partially positioned within at least one trench in a surface of the first wafer. 10. A device having embedded metallic structures in a glass comprising: a first wafer having at least one first wafer via filled with conductive material; at least one conductive trace formed on the first wafer, the at least one conductive trace being in contact with the at least one first wafer via filled with the conductive material; a planarized insulation layer formed over the first wafer and at least one conductive trace, the planarized insulation layer further having at least one insulation layer via that provides a path to a portion of the at least one conductive trace, at least one conductive contact layer within at least a portion of the at least one insulation layer via, the at least one conductive contact layer being in contact with the at least one conductive trace: and a second wafer laser bonded to the planarized insulation layer, the second wafer having at least one non-filled via aligned with the at least one conductive contact layer, and at least one antennal structure in the first wafer, the antenna structure comprising a metal filled channel in the first wafer in contact with a second first wafer via filled with conductive material.

Assignees

Inventors

Classifications

  • used as a support during the manufacture of self-supporting substrates · CPC title

  • using temporarily an auxiliary support · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • comprising multiple insulating layers · CPC title

  • H10W70/692Primary

    Ceramics or glasses · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9832867B2 cover?
A device having embedded metallic structures in a glass is provided. The device includes a first wafer, at least one conductive trace, a planarized insulation layer and a second wafer. The first wafer has at least one first wafer via that is filled with conductive material. The at least one conductive trace is formed on the first wafer. The at least one conductive trace is in contact with the a…
Who is the assignee on this patent?
Medtronic Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/692. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).