Multilayered substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9832866-B2
Application number	US-201615196857-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jun 29, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A multilayered substrate includes unit substrates laminated in a direction of thickness thereof, and the unit substrates include a photosensitive insulating layer, a conductive pattern disposed in the photosensitive insulating layer, and a bump penetrating into the photosensitive insulating layer and providing an interlayer connection to the conductive pattern.

First claim

What is claimed is:

1. A multilayered substrate comprising a plurality of unit substrates laminated in a direction of thickness thereof,
wherein the unit substrates each comprise:
a photosensitive insulating layer;
a conductive pattern embedded in the photosensitive insulating layer and having one surface thereof exposed through one surface of the photosensitive insulating layer; and
a bump penetrating into the photosensitive insulating layer and providing an interlayer connection to the conductive pattern, and

wherein the bump comprises:
a copper layer making contact with the conductive pattern of one of the unit substrates; and
a solder layer formed on the copper layer and making contact with the conductive pattern of another of the unit substrates.

2. The multilayered substrate of claim 1 , further comprising:
a first metal pattern disposed above an uppermost unit substrate of the unit substrates;
a first insulating layer laminated below a lowermost unit substrate of the unit substrates;
a second metal pattern disposed on a lower surface of the first insulating layer; and
a via disposed in the first insulating layer and connecting the conductive pattern of the lowermost unit substrate of the unit substrates with the second metal pattern.

3. The multilayered substrate of claim 2 , wherein the first insulating layer comprises a photosensitive resin, and
wherein the via and the bump comprise a same material.

4. The multilayered substrate of claim 2 , further comprising a solder resist disposed on the first metal pattern and the second metal pattern.

5. The multilayered substrate of claim 2 , further comprising:
a second insulating layer disposed above the uppermost unit substrate and covering the first metal pattern; and
a third metal pattern disposed on the second insulating layer.

6. The multilayered substrate of claim 5 , wherein the first insulating layer and the second insulating layer each comprise a resin impregnated with a fiber stiffener.

7. The multilayered substrate of claim 5 , further comprising a solder resist disposed on the second metal pattern or the third metal pattern.

Assignees

• Samsung Electro Mech

Inventors

• Ahn Seok-Hwan
• Hwang Mi-Sun
• Ko Young-Gwan
• Bae Jong-Seok
• Kang Myung-Sam

Classifications

• H05K3/12

  using {thick film techniques, e.g.} printing techniques to apply the conductive material {or similar techniques for applying conductive paste or ink patterns} · CPC title

• H05K1/09

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title

• H05K3/4007

  Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465) · CPC title

• H05K2203/043

  Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste · CPC title

• H05K3/007 Primary

  Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence) · CPC title