Phased clock error handling

Patent metadata

Field	Value
Publication number	US-9832013-B2
Application number	US-201615012518-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Feb 1, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.

First claim

What is claimed is:

1. A phased clock error handling system comprising:
a unit interval (UI) clock circuit comprising:
N phased clock inputs, each coupled with an output of a respective one of a plurality of phased clocks; and
N UI clock signal outputs, each comprising a respective 1/N duty cycle pulse signal generated from a respective pair of the phased clock inputs by logically combining one of the respective pair with a complement of the other of the respective pair, the respective pair being phase-delayed each from the other by 360/N degrees,
such that any Mth UI clock signal output of the N UI clock signal outputs is offset from any (M+1)st UI clock signal output of the N UI clock signal outputs by 360/N degrees and each falling edge of the respective pulse signal of the Mth UI clock signal output is coincident with each rising edge of the respective pulse signal of the (M+1)st UI clock signal output, where M is an integer; and

a phased clock error (PCE) detector circuit comprising:
a UI clock selector coupled with the N UI clock signal outputs;
a digital sampler having a selected UI clock input and a clock pulse width output, the selected UI clock input coupled with the UI clock selector to receive a selected one of the N UI clock signal outputs; and
a PCE output that indicates a detected PCE when a first clock pulse width differs from a second clock pulse width by more than a predetermined threshold amount, wherein the first clock pulse width is received from the clock pulse width output in response to asynchronously digitally sampling the Mth UI clock signal output, and the second clock pulse width is received from the clock pulse width output in response to asynchronously digitally sampling the (M+1)st UI clock signal output.

2. The system of claim 1 , wherein the PCE detector circuit further comprises:
an up/down counter having a sample input coupled with the clock pulse width output, and a count output coupled with the PCE output,
wherein, after digitally sampling the Mth UI clock signal output, the count output represents a value associated with the first clock pulse width,
wherein, after digitally sampling the (M+1)st UI clock signal output, the count output represents a value associated with a difference between the first clock pulse width and the second clock pulse width, and
wherein the PCE output indicates the detected PCE when the count output represents a value that falls outside a guard band tolerance corresponding to the predetermined threshold amount.

3. The system of claim 1 , wherein the PCE detector circuit further comprises:
a sampling schema controller having a schema output coupled with the UI clock selector, and a schema input coupled with the PCE output, such that the N UI clock signal outputs are selectable by the sampling schema controller according to the PCE output.

4. The system of claim 1 , further comprising:
a PCE correction circuit comprising a plurality of selectable delay circuit paths selected according to the PCE output, such that the selected delay circuit path introduces signal delay to the UI clock circuit, thereby shifting the coincident rising and falling edges of the N UI clock signal outputs.

5. The system of claim 4 , wherein the PCE correction circuit comprises:
a PCE correction sub-circuit having:
a detect input coupled with the PCE output; and
a delay code output coupled with the plurality of selectable delay circuit paths,

wherein the plurality of selectable delay circuit paths is selectable according to the delay code output.

6. The system of claim 4 , wherein the PCE correction circuit comprises:
a first delay stage comprising a multiplexer having a plurality of first-stage inputs, each coupled with a different respective number of delay elements, a first select input, and a first-stage output that is a selected one of the multiplexer inputs according to the first select input.

7. The system of claim 6 , wherein the PCE correction circuit further comprises:
a second delay stage comprising a variable capacitance having a second-stage input coupled with the first-stage output, a second select input, and a second-stage output that is a capacitively delayed version of the second-stage input according to a capacitance selected by the second select input.

8. The system of claim 1 , wherein:
the UI clock circuit further comprises N sub-circuits, each having:
a first sub-circuit input coupled to a respective first of the N phased clock inputs,
a second sub-circuit input coupled to a respective second of the N phased clock inputs, and
a respective one of the N UI clock signal outputs, the UI clock signal output being HIGH only when the first sub-circuit input is HIGH and the second sub-circuit input is LOW.

9. The system of claim 1 , further comprising:
a clock output circuit coupled with the N UI clock signal outputs and having a clock signal output generated from a combination of the N UI clock signal outputs.

10. The system of claim 9 , wherein:
each of the N phased clock inputs is at a first data rate; and
each of the N UI clock signal outputs is at a second data rate that is N times the first data rate.

11. A method for phased clock error handling, the method comprising:
generating N unit interval (UI) clock signals, each from a respective pair of N received phased clock inputs, to have a respective 1/N duty cycle pulse signal generated by logically combining one of the respective pair with a complement of the other of the respective pair, the respective pair being phase-delayed each from the other by 360/N degrees,
such that any Mth UI clock signal of the N UI clock signals is offset from any (M+1)st UI clock signal of the N UI clock signals by 360/N degrees and each falling edge of the respective pulse signal of the Mth UI clock signal is coincident with each rising edge of the respective pulse signal of the (M+1)st UI clock signal, where M is an integer;
selecting a first UI clock signal and a second UI clock signal from the plurality of N generated UI clock signals, such that the first and second selected UI clock signals share a clock pulse edge;
first asynchronously sampling the first selected UI clock signal, digitally, to determine a first clock pulse width;
second asynchronously sampling the second selected UI clock signal, digitally, to determine a second clock pulse width; and
detecting whether there is a phased clock error (PCE) in response to determining that the first and second clock pulse widths differ by more than a predetermined threshold amount.

12. The method of claim 11 , wherein:
the first sampling comprises incrementing a counter for each of a plurality of samples of the first selected UI clock signal indicating a logical HIGH;
the second sampling comprises decrementing the counter for each of a plurality of samples of the second selected UI clock signal indicating a logical HIGH; and
the detecting comprises determining whether the counter, after sampling the second selected UI clock signal, indicates a value that falls outside a guard band tolerance corresponding to the predetermined threshold amount.

13. The method of claim 11 , wherein the generating comprises:
adjusting a signal delay to at least one of the first or second selected UI clock signals in response to the detecting, the adjusting shifting the shared clock pulse edge.

14. The method of claim 13 , further comprising:
equaling the first and second selected UI clock signals by iteratively performing the selecting, the first sampling, the second sampling, the detecting, and the adjusting until the detecting determines that the first and seco

Assignees

• Oracle Int Corp

Inventors

• Chen Ben Li
• Qin Zuxu
• Edelkhani Nima

Classifications

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K5/151

  with two complementary outputs · CPC title

• H03K23/58

  Gating or clocking signals not applied to all stages, i.e. asynchronous counters (H03K23/74 - H03K23/84 take precedence) · CPC title

• H04L7/0337 Primary

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0037

  Delay of clock signal · CPC title