Semiconductor integrated circuit, variable gain amplifier, and sensing system

Patent metadata

Field	Value
Publication number	US-9831842-B2
Application number	US-201514865204-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Oct 1, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Provided is a semiconductor integrated circuit including a pad Pd 1 provided on one end side of a resistive element R 1 externally provided, a pad Pd 5 provided on a different end side of the resistive element R 1; an operation amplifier A 1 , a signal line L 11 wired between an output terminal of the operation amplifier A 1 and the pad Pd 1 , a signal line L 21 wired between an inverting input terminal of the operation amplifier A 1 and the pad Pd 5 , a ESD protection element r 11 provided to the signal line L 11 , and a signal line L 31, through which a voltage signal of the pad Pd 1 is transmitted. The signal line L 31 is connected to the pad Pd 1.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first pad provided on one end side of a first resistive element externally provided;
a second pad provided on a different end side of the first resistive element;
an operation amplifier;
a first signal line wired between an output terminal of the operation amplifier and the first pad;
a second signal line wired between one input terminal of the operation amplifier and the second pad;
a first ESD (Electrostatic Discharge) protection element provided to the first signal line; and
a third signal line, through which a voltage signal of the first pad is transmitted, the third signal line being connected to the first pad,
a plurality of first pads provided on one end side of each of a plurality of first resistive elements externally provided;
the second pad provided on a different end side of each of the plurality of first resistive elements;
a plurality of first signal lines wired between the output terminal of the operation amplifier and the plurality of first pads, respectively;
a plurality of first switches, one of which is selectively turned on, the plurality of first switches being provided on the plurality of first signal lines, respectively;
a plurality of first ESD protection elements provided to the plurality of first signal lines, respectively;
a plurality of third signal lines, through which voltage signals of the plurality of first pads are transmitted, the plurality of third signal lines being connected to the plurality of first pads, respectively; and
a plurality of second switches, one of which is selectively turned on, the plurality of second switches being provided on the plurality of third signal lines, respectively.

2. The semiconductor integrated circuit according to claim 1 , wherein
the one input terminal of the operation amplifier is an inverting input terminal,
a reference voltage is supplied to a non-inverting input terminal as a different input terminal of the operation amplifier, and
an input current supplied to the second pad is converted to the voltage signal.

3. A semiconductor integrated circuit comprising:
a first pad provided on one end side of a first resistive element externally provided;
a second pad provided on a different end side of the first resistive element;
an operation amplifier;
a first signal line wired between an output terminal of the operation amplifier and the first pad;
a second signal line wired between one input terminal of the operation amplifier and the second pad;
a first ESD (Electrostatic Discharge) protection element provided to the first signal line; and
a third signal line, through which a voltage signal of the first pad is transmitted, the third signal line being connected to the first pad,
the first pad provided on one end side of each of a plurality of first resistive elements externally provided;
a plurality of second pads provided on a different end side of each of the plurality of first resistive elements;
a plurality of second signal lines wired between the one input terminal of the operation amplifier and the plurality of second pads, respectively; and
a plurality of third switches, one of which is selectively turned on, the plurality of third switches being provided on the plurality of second signal lines, respectively.

4. The semiconductor integrated circuit according to claim 3 , wherein
the one input terminal of the operation amplifier is an inverting input terminal,
an input voltage is supplied to a non-inverting input terminal as a different input terminal of the operation amplifier, and
a reference voltage is supplied to the different end side of each of the plurality of first resistive elements through a second resistive element.

5. The semiconductor integrated circuit according to claim 3 , wherein
the one input terminal of the operation amplifier is an inverting input terminal,
a reference voltage is supplied to a non-inverting input terminal as a different input terminal of the operation amplifier, and
an input voltage is supplied to the different end side of each of the plurality of first resistive elements through a second resistive element.

6. The semiconductor integrated circuit according to claim 1 , further comprising a subsequent stage circuit to which a voltage signal of the first pad which is transmitted through the third signal line is supplied.

7. The semiconductor integrated circuit according to claim 6 , wherein the subsequent stage circuit is an AD converter.

8. The semiconductor integrated circuit according to claim 1 , further comprising a voltage follower provided on the third signal line.

9. A semiconductor integrated circuit comprising:
a first pad provided on one end side of a first resistive element externally provided;
a second pad provided on a different end side of the first resistive element;
an operation amplifier;
a first signal line wired between an output terminal of the operation amplifier and the first pad;
a second signal line wired between one input terminal of the operation amplifier and the second pad;
a first ESD (Electrostatic Discharge) protection element provided to the first signal line; and
a third signal line, through which a voltage signal of the first pad is transmitted, the third signal line being connected to the first pad,
a plurality of pads as the first and second pads;
a plurality of first signal lines wired between the output terminal of the operation amplifier and the plurality of pads, respectively;
a plurality of first switches provided on the plurality of first signal lines, respectively;
a plurality of second signal lines wired between the one input terminal of the operation amplifier and the plurality of pads, respectively;
a plurality of third switches provided on the plurality of second signal lines, respectively;
a plurality of fourth signal lines wired between a different input terminal of the operation amplifier and the plurality of pads, respectively;
a plurality of fourth switches provided on the plurality of fourth signal lines, respectively;
a plurality of third signal lines, to which voltage signals of the plurality of pads are transmitted, the plurality of third signal lines being connected to the plurality of pads, respectively; and
a plurality of second switches provided on the plurality of third signal lines, respectively.

10. A variable gain amplifier comprising:
the plurality of first resistive elements; and
the semiconductor integrated circuit according to claim 2 .

11. A variable gain amplifier comprising:
the plurality of first resistive elements;
the second resistive element; and
the semiconductor integrated circuit according to claim 4 .

12. A variable gain amplifier comprising:
the plurality of first resistive elements;
the second resistive element; and
the semiconductor integrated circuit according to claim 5 .

13. A sensing system comprising:
a sensor that outputs the input current as a measurement result;
the plurality of first resistive elements; and
the semiconductor integrated circuit according to claim 2 .

14. A sensing system comprising:
a sensor that outputs the input voltage as a measurement result;
the plurality of first resistive elements;
the second resistive element; and
the semiconductor integrated circuit according to claim 4 .

15. A sensing system comprising:
a sensor that outputs the input voltage as a measurement result;
the plurality of first resistive elements;
the second resistive element; and
the semiconductor integrated circuit according to claim 5 .

Assignees

• Renesas Electronics Corp

Inventors

• Kiritani Masahide

Classifications

• H03F3/50

  Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower · CPC title

• H03F2203/45601

  the IC comprising one or more passive resistors by feedback · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45528

  the FBC comprising one or more passive resistors and being coupled between the LC and the IC · CPC title

• H03F3/08

  controlled by light · CPC title