Self-balanced modulation and magnetic rebalancing method for parallel multilevel inverters

Patent metadata

Field	Value
Publication number	US-9831800-B2
Application number	US-201615297828-A
Country	US
Kind code	B2
Filing date	Oct 19, 2016
Priority date	Apr 21, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A self-balanced modulation method and a closed-loop magnetic flux rebalancing control method for parallel multilevel inverters. The combination of the two methods provides for balancing of the magnetic flux of the inter-cell transformers (ICTs) of the parallel multilevel inverters without deteriorating the quality of the output voltage. In various embodiments a parallel multi-level inverter modulator is provide including a multi-channel comparator to generate a multiplexed digitized ideal waveform for a parallel multi-level inverter and a finite state machine (FSM) module coupled to the parallel multi-channel comparator, the FSM module to receive the multiplexed digitized ideal waveform and to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter. The system and method provides for optimization of the output voltage spectrum without influence the magnetic balancing.

First claim

What is claimed is:

1. A parallel multi-level inverter modulator, the modulator comprising:
a multi-channel comparator to generate a multiplexed digitized ideal waveform for a parallel multi-level inverter; and
a finite state machine (FSM) module coupled to the parallel multi-channel comparator, the FSM module to receive the multiplexed digitized ideal waveform and to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter.

2. The modulator of claim 1 , wherein the FSM module further comprises circuitry and memory for performing a predetermined logic operation on the multiplexed digitized ideal waveform to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter.

3. The modulator of claim 1 , wherein the multi-channel comparator further comprises:
a pre-processing module to receive a reference waveform and to generate a plurality of modified reference waveforms;
a plurality of comparators coupled to the pre-processing module, each of the plurality of comparators to receive one of the plurality of modified reference waveforms, to compare the modified reference waveform to a carrier waveform and to generate an output signal; and
a level encoder coupled to the plurality of comparators, the level encoder to receive the output signal from each of the comparators and to generate the multiplexed digitized ideal waveform comprising an instantaneous level number for each level of the parallel multi-level inverter.

4. The modulator of claim 3 , wherein each of the plurality of modified reference waveforms are generated from a different portion of the reference waveform.

5. The modulator of claim 1 , further comprising:
a closed-loop rebalancing control module coupled to the FSM module.

6. The modulator of claim 5 , wherein the closed-loop rebalancing control module further comprises a closed-loop rebalancing control module for each level the parallel multi-level inverter.

7. The modulator of claim 5 , wherein the closed-loop rebalancing control module further comprises at least one differential current sensor for measuring a differential current between two phase legs of the parallel multi-level inverter.

8. The modulator of claim 7 , wherein the closed-loop rebalancing control module further comprises circuitry for adjusting a ratio between opposite switching state pairs of the two phase legs of the parallel multi-level inverter based upon the differential current between the two phase legs of the parallel multi-level inverter.

9. A system comprising:
a reference waveform generator;
a parallel multi-level inverter modulator coupled to the reference waveform generator, the modulator comprising;
a multi-channel comparator to generate a multiplexed digitized ideal waveform for a parallel multi-level inverter;
a finite state machine (FSM) module coupled to the parallel multi-channel comparator, the FSM module to receive the multiplexed digitized ideal waveform and to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter; and

a plurality of inverter phase legs and inter-cell transformers (ICTs) coupled to the FSM module.

10. The system of claim 9 , wherein the FSM module further comprises circuitry and memory for performing a predetermined logic operation on the multiplexed digitized ideal waveform to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter.

11. The system of claim 9 , wherein the multi-channel comparator further comprises:
a pre-processing module to receive a reference waveform and to generate a plurality of modified reference waveforms;
a plurality of comparators coupled to the pre-processing module, each of the plurality of comparators to receive one of the plurality of modified reference waveforms, to compare the modified reference waveform to a carrier waveform and to generate an output signal; and
a level encoder coupled to the plurality of comparators, the level encoder to receive the output signal from each of the comparators and to generate the multiplexed digitized ideal waveform comprising an instantaneous level number for each level of the parallel multi-level inverter.

12. The system of claim 11 , wherein each of the plurality of modified reference waveforms are generated from a different portion of the reference waveform.

13. The system of claim 9 , further comprising:
a closed-loop rebalancing control module coupled to the FSM module.

14. The system of claim 13 , wherein the closed-loop rebalancing control module further comprises a closed-loop rebalancing control module for each level of the parallel multi-level inverter.

15. The system of claim 13 , wherein the closed-loop rebalancing control module further comprises at least one differential current sensor for measuring a differential current between two phase legs of the parallel multi-level inverter.

16. The system of claim 15 , wherein the closed-loop rebalancing control module further comprises circuitry for adjusting a ratio between opposite switching state pairs of the two phase legs of the parallel multi-level inverter based upon the differential current between the two phase legs of the parallel multi-level inverter.

17. The system of claim 9 , further comprising an output filter coupled to the plurality of inverter phase legs.

18. A modulation method for a parallel multilevel inverter, the method comprising:
receiving a reference waveform at a multi-channel comparator of a parallel multi-level inverter modulator;
generating a multiplexed digitized ideal waveform at the multi-channel comparator for each level of a parallel multi-level inverter associated with the parallel multi-level inverter modulator;
receiving the multiplexed digitized ideal waveform at a finite state machine (FSM) module of the parallel multi-level inverter modulator; and
generating a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter.

19. The method of claim 18 , further comprising:
measuring a differential current between two phase legs of the parallel multi-level inverter; and
adjusting a ratio between opposite switching state pairs of the two phase legs of the parallel multi-level inverter based upon the differential current between the two phase legs of the parallel multi-level inverter to re-balance a magnetic flux of the parallel multi-level inverter.

20. The method of claim 18 , wherein generating a multiplexed digitized ideal waveform a the multi-channel comparator further comprises:
pre-processing the reference waveform to generate a plurality of modified reference waveforms, wherein each of the plurality of modified reference waveforms are generated from a different portion of the sinusoidal reference waveform;
comparing each one of the plurality of modified reference waveforms to carrier waveform to generate an output signal; and
level encoding the output signal to generate the multiplexed digitized ideal waveform comprising an instantaneous level number for each level of the parallel multi-level inverter.

Assignees

• Univ Florida State Res Found Inc

Inventors

• Li Hui
• Shi Yanjun

Classifications

• H02M7/487

  Neutral point clamped inverters · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M7/49 Primary

  Combination of the output voltage waveforms of a plurality of converters · CPC title

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title