Nanoporous metal-oxide memory

Patent metadata

Field	Value
Publication number	US-9831424-B2
Application number	US-201514809770-A
Country	US
Kind code	B2
Filing date	Jul 27, 2015
Priority date	Jul 25, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A nanoporous (NP) memory may include a non-porous layer and a nanoporous layer sandwiched between the bottom and top electrodes. The memory may be free of diodes, selectors, and/or transistors that may be necessary in other memories to mitigate crosstalk. The nanoporous material of the nanoporous layer may be a metal oxide, metal chalcogenide, or a combination thereof. Further, the memory may lack any additional components. Further, the memory may be free from requiring an electroformation process to allow switching between ON/OFF states.

First claim

What is claimed is:

1. A memory system comprising:
at least one memory cell, wherein the at least one memory cell comprises,
a substrate;
a bottom electrode deposited on the substrate;
a non-porous layer deposited on the bottom electrode;
a nanoporous (NP) layer deposited on the non-porous layer, wherein the NP layer is a metal oxide or metal chalcogenide, and the all pores of the NP layer are unfilled; and
a top electrode deposited on the NP layer, wherein the top electrode interfaces with the NP layer, and the non-porous layer and the NP layer are sandwiched between the bottom and top electrodes.

2. The system of claim 1 , wherein the memory system is free of diodes, selectors, and transistors.

3. The system of claim 2 , wherein the at least one memory cell further comprises an interlayer between the top electrode and the NP layer.

4. The system of claim 3 , wherein the at least one memory cell consists of only the substrate, the bottom electrode, the non-porous layer, the nanoporous layer, the interlayer, and the top electrode.

5. The system of claim 1 , wherein the NP layer is Ta 2 O 5-x where 0≦x<5.

6. The system of claim 1 , wherein oxygen vacancies or chalcogenide vacancies in the NP layer increase towards the bottom electrode.

7. The system of claim 1 , wherein pore radius sizes of pores of the NP layer are equal to or between 2-100 nm.

8. The system of claim 1 , wherein the at least one memory cell is free from requiring an electroforming process.

9. The system of claim 1 , wherein a positive or negative voltage pulse of 10 V or less sets/resets the at least one memory cell to ON/OFF states.

10. The system of claim 1 , wherein the at least one memory cell is capable of being switched between ON/OFF states with a current equal to or less than 100 μA.

11. The system of claim 1 , wherein R on is equal to or greater than 10 4 or R off is equal to or greater than 10 5 .

12. The system of claim 1 , wherein the at least one memory cell has an ON and OFF ratios with a factor of 5 or greater.

13. The system of claim 1 , wherein the memory system has an array density of 100 or greater.

Assignees

• Tour James M
• Wang Gunuk
• Yang Yang
• Univ Rice William M

Inventors

• Tour James M
• Wang Gunuk
• Yang Yang

Classifications

• H01L45/08 Primary

  Electricity · mapped topic

• H01L27/2472

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/1633

  Electricity · mapped topic