LED array

US9831383B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9831383-B2
Application numberUS-201314071106-A
CountryUS
Kind codeB2
Filing dateNov 4, 2013
Priority dateNov 18, 2011
Publication dateNov 28, 2017
Grant dateNov 28, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. An LED array comprising: a base substrate; a bonding layer on the base substrate, wherein the bonding layer comprises a polymer; an array of separate LED devices on the bonding layer, wherein each of the LED devices includes a top doped layer, a bottom doped layer doped with an opposite dopant type than the top doped layer, and a quantum well layer between the top doped layer and the bottom doped layer; an array of bottom conductive contacts between the array of separate LED devices and the bonding layer, wherein each of the bottom conductive contacts is formed on a corresponding bottom doped layer of a corresponding separate LED device; a continuous insulating material layer on the bonding layer and between the array of separate LED devices and the bonding layer, wherein the continuous insulating material layer spans laterally between each of the separate LED devices in the array of separate LED devices and underneath each of the bottom conductive contacts in the array of bottom conductive contacts; array of openings in the continuous insulating material layer underneath the array of separate LED devices; wherein the bonding layer occupies the array of openings in the continuous insulating material and the array of bottom conductive contacts are on the bonding layer; wherein the bonding layer comprises a flat bottom surface that completely spans between and directly underneath each of the separate LED devices in the array of separate LED devices; and wherein the top doped layers of the array of separate LED devices are not electrically connected to one another. 2. The LED array of claim 1 , wherein the bonding layer is in direct contact with the array of bottom conductive contacts. 3. The LED array of claim 2 , wherein the bottom conductive contacts are wider than the openings in the continuous insulator layer. 4. The LED array of claim 1 , wherein a topography of the continuous insulating material layer is embedded into the bonding layer. 5. The LED array of claim 1 , wherein the continuous insulating material layer is an oxide or nitride. 6. The LED array of claim 1 , wherein the continuous insulating material layer is 0.1 μm to 1.0 μm thick. 7. The LED array of claim 1 , wherein the bottom conductive contacts are reflective to the visible spectrum. 8. The LED array of claim 1 , wherein each of the bottom conductive contacts comprises a metallization stack.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • of die-attach connectors · CPC title

  • Apparatus therefor · CPC title

  • Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates · CPC title

  • H10H20/018Primary

    Bonding of wafers · CPC title

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Frequently asked questions

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What does patent US9831383B2 cover?
A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and …
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H10H20/018. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).