Transistor with MIS connections and fabricating process

Patent metadata

Field	Value
Publication number	US-9831319-B2
Application number	US-201615058615-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Mar 3, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

First claim

The invention claimed is:

1. A field-effect transistor, comprising:
a source, drain, and channel formed in a semiconductor layer;
a gate stack disposed above the channel and comprising a metal electrode, a first layer of electrical insulator disposed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode;
a metal contact disposed plumb with the source or the drain and at least partially plumb with said gate stack; and
a third layer of electrical insulator disposed between said metal contact and said source or said drain, said third layer of electrical insulator at least partially covering said gate stack and not extending laterally beyond an end of the source or the drain in a direction parallel to a surface of the semiconductor layer.

2. The transistor according to claim 1 , wherein said gate stack includes at least one spacer disposed laterally relative to said first layer of electrical insulator, relative to said metal electrode, and relative to said second layer of electrical insulator, said metal contact and said third layer of electrical insulator being disposed at least partially plumb with said at least one spacer.

3. The transistor according to claim 1 , wherein said third layer of electrical insulator at least partially covers said second layer of electrical insulator.

4. The transistor according to claim 1 , wherein said third layer of electrical insulator includes two superposed films made of different materials.

5. The transistor according to claim 1 , wherein said source and said drain in the semiconductor layer are not alloyed with a metal.

6. The transistor according to claim 1 , wherein said third layer of electrical insulator has a thickness comprised between 0.8 nm and 3 nm from a level of contact with said source or said drain.

7. The transistor according to claim 1 , further comprising:
another metal contact disposed plumb with the other of the source or the drain, and at least partially plumb with said gate stack; and
a fourth layer of electrical insulator disposed between said another metal contact and said other of the source or the drain, said fourth layer of electrical insulator at least partially covering said gate stack and not extending laterally beyond an end of the source or the drain in a direction parallel to a surface of the semiconductor layer.

8. A process for fabricating a field-effect transistor, comprising:
providing an assembly comprising:
a semiconductor layer in which a source, drain, and channel are formed:
a gate stack disposed above the channel and comprising a metal electrode, a first layer of electrical insulator disposed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; and
a third layer of electrical insulator disposed between a metal contact and said source and said drain, said third layer of electrical insulator at least partially covering said gate stack and not extending laterally beyond an end of the source or the drain in a direction parallel to a surface of the semiconductor layer; and

forming said metal contact on said third layer of electrical insulator plumb with the source or the drain and at least partially plumb with said gate stack.

9. The process according to claim 8 , wherein:
said provided gate stack includes at least one spacer disposed laterally relative to said first layer of electrical insulator, relative to said metal electrode, and relative to said second layer of electrical insulator, and
said metal contact and said third layer of electrical insulator being formed at least partially plumb with said at least one spacer.

10. The process according to claim 9 , further comprising:
forming a metal pad disposed laterally relative to said at least one spacer prior to forming said metal electrode, wherein the metal electrode is formed by removing a portion of the metal pad that is disposed laterally relative to said at least one spacer,
wherein the second layer of electrical insulator is formed by depositing said second layer of electrical insulator on said metal electrode.

11. The process according to claim 8 , wherein:
providing said assembly further comprises providing a fourth insulating layer including a through-aperture produced plumb with the gate stack and plumb with the source and the drain, and forming grooves on either side of the gate stack and being delimited laterally by said fourth insulating layer, a bottom of said formed grooves being delimited by said source and said drain, respectively,
said third layer of electrical insulator is formed so as to cover at least the bottom of said formed grooves, and
at least a first portion of said metal contact is formed by transferring metal into at least one of said formed grooves.

12. The process according to claim 11 , wherein said third layer of electrical insulator is formed so as to cover said fourth insulating layer and said gate stack, the process further comprising:
removing said third layer of electrical insulator from an upper face of the fourth insulating layer and the gate stack; and then
forming a second portion of said metal contact by transferring metal into contact with said first portion of said metal contact.

13. The process according claim 8 , wherein:
providing said assembly further comprises providing a fourth insulating layer including through-apertures produced plumb with the source and the drain, respectively, and forming grooves on either side of the gate stack and being delimited laterally by said fourth insulating layer, a bottom of said formed grooves being delimited by said source and by said drain, respectively,
said third layer of electrical insulator is formed so as to cover a portion of the fourth insulating layer covering the bottom of said formed grooves and sidewalls of said formed grooves and covering at least partially the gate stack, and
said metal contact is formed by transferring metal into at least one of said formed grooves.

14. The process according to claim 13 , further comprising, subsequent to said transferring metal, removing said third layer of electrical insulator from an upper face of the fourth insulating layer.

Assignees

• Commissariat Energie Atomique

Inventors

• Borrel Julien
• Hutin Louis
• Morand Yves
• Nemouchi Fabrice
• Niebojewski Heimanu

Classifications

• H10P14/42

  using a gas or vapour · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/76897

  Electricity · mapped topic