Array substrate having an electro-static discharge unit, electro-static discharge method thereof and display device

Patent metadata

Field	Value
Publication number	US-9831277-B2
Application number	US-201615222136-A
Country	US
Kind code	B2
Filing date	Jul 28, 2016
Priority date	Oct 16, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

An array substrate, an electro-static discharge method thereof and a display device are disclosed. The array substrate includes: a plurality of data lines, a plurality of gate lines, a power signal line, a charge release signal line, a plurality of electro-static discharge units and at least one short circuit ring unit. The charge release signal line and the power signal line are disposed in parallel, two electro-static discharge units are disposed between them to form an electro-static discharge circuit, each gate line and/or each data line is connected with the charge release signal line by one electro-static discharge unit; the short circuit ring unit is connected between the charge release signal line and the power signal line.

First claim

What is claimed is:

1. An array substrate, comprising: a plurality of data lines, a plurality of gate lines, a power signal line, a charge release signal line, a plurality of electro-static discharge units and at least one short circuit ring unit, wherein,
the charge release signal line and the power signal line are disposed in parallel, two of the electro-static discharge units are disposed between the charge release signal line and the power signal line to form an electro-static discharge circuit, each of the gate lines and/or each of the data lines is connected with the charge release signal line by one of the electro-static discharge units;
a first control terminal and a first input terminal of the short circuit ring unit are connected with the charge release signal line, a first output terminal is connected with the power signal line, a second control terminal and a second input terminal are connected with the power signal line, and a second output terminal is connected with the charge release signal line.

2. The array substrate according to claim 1 , wherein, two adjacent gate lines of the gate lines and/or two adjacent data lines of the data lines correspond to one short circuit ring unit.

3. The array substrate according to claim 2 , wherein, the short circuit ring unit comprises: a first switching transistor and a second switching transistor,
a gate electrode and a source electrode of the first switching transistor are both connected with the charge release signal line, a drain electrode of the first switching transistor is connected with the power signal line; and
a gate electrode and a source electrode of the second switching transistor are both connected with the power signal line, a drain electrode of the second switching transistor is connected with the charge release signal line.

4. The array substrate according to claim 1 , wherein, at least one of the electro-static discharge units comprises: a third switching transistor and a fourth switching transistor,
the electro-static discharge unit, the power signal line and the charge release signal line form an electro-static discharge circuit, a gate electrode and a source electrode of the third switching transistor are both connected with the power signal line, and a drain electrode of the third switching transistor is connected with the charge release signal line; a gate electrode and a source electrode of the fourth switching transistor are both connected with the charge release signal line, and a drain electrode of the fourth switching transistor is connected with the power signal line; or
the electro-static discharge unit connects the gate line and the charge release signal line, the gate electrode and the source electrode of the third switching transistor are both connected with the gate line, and the drain electrode of the third switching transistor is connected with the charge release signal line; the gate electrode and the source electrode of the fourth switching transistor are both connected with the charge release signal line, and the drain electrode of the fourth switching transistor is connected with the gate line; or
the electro-static discharge unit connects the data line and the charge release signal line, the gate electrode and the source electrode of the third switching transistor are both connected with the data line, and the drain electrode of the third switching transistor is connected with the charge release signal line; the gate electrode and the source electrode of the fourth switching transistor are both connected with the charge release signal line, and the drain electrode of the fourth switching transistor is connected with the data line.

5. The array substrate according to claim 1 , wherein, at least one of the electro-static discharge units comprises: a fifth switching transistor, a first capacitor and a second capacitor,
the electro-static discharge unit, the power signal line and the charge release signal line form an electro-static discharge circuit, a gate electrode of the fifth switching transistor connects with one end of the first capacitor and one end of the second capacitor respectively, a source electrode of the fifth switching transistor connects with the other end of the first capacitor and the power signal line respectively, a drain electrode of the fifth switching transistor connects with the other end of the second capacitor and the charge release signal line respectively; or
the electro-static discharge unit connects the gate line and the charge release signal line, the gate electrode of the fifth switching transistor connects with one end of the first capacitor and one end of the second capacitor respectively, the source electrode of the fifth switching transistor connects with the other end of the first capacitor and the gate line, and the drain electrode of the fifth switching transistor connects with the other end of the second capacitor and the charge release signal line; or
the electro-static discharge unit connects the data line and the charge release signal line, the gate electrode of the fifth switching transistor connects with one end of the first capacitor and one end of the second capacitor respectively, the source electrode of the fifth switching transistor connects with the other end of the first capacitor and the data line respectively, and the drain electrode of the fifth switching transistor connects with the other end of the second capacitor and the charge release signal line respectively.

6. The array substrate according to claim 1 , further comprising an organic electroluminescent structure comprising a cathode; wherein, the power signal line and the cathode of the organic electroluminescent structure are connected.

7. An electro-static discharge method of the array substrate according to claim 1 comprising:
upon static charges being generated on the power signal line, releasing the static charges to the electro-static discharge circuit through the short circuit ring unit; and
upon static charges being generated on the gate line or the data line, releasing the static charges to the charge release signal line through the electro-static discharge unit connected with the gate line or the data line, and releasing the static charges to the power signal line through the short circuit ring unit adjacent to the gate line or the data line.

8. An organic electroluminescent display panel, comprising the array substrate according to claim 1 .

9. A display device, comprising the organic electroluminescent display panel according to claim 8 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Gai Cuili
• Li Quanhu

Classifications

• H01L27/0266

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title