Negative capacitance FinFET device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9831239-B1
Application number	US-201715475404-A
Country	US
Kind code	B1
Filing date	Mar 31, 2017
Priority date	Dec 30, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Provided is a negative capacitance FinFET device including a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate and a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance. The FinFET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode and the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.

First claim

We claim:

1. A negative capacitance FinFET device comprising:
a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate; and
a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance,
wherein the FinFET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode, and
the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.

2. The negative capacitance FinFET device of claim 1 ,
wherein the extension length is set to be in a range from 80 nm to 150 nm.

3. The negative capacitance FinFET device of claim 1 ,
wherein the extension length is set to be in a range from 120 nm to 150 nm.

4. The negative capacitance FinFET device of claim 3 ,
wherein the size of the hysteresis window in the negative capacitance FinFET device is from 0.4 V to 0.5 V.

5. The negative capacitance FinFET device of claim 1 ,
wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 60 mV/decade at room temperature.

6. The negative capacitance FinFET device of claim 1 ,
wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 20 mV/decade at room temperature.

7. The negative capacitance FinFET device of claim 1 ,
wherein the ferroelectric negative capacitor includes:
a substrate;
a first electrode layer formed on the substrate;
a ferroelectric layer formed on the first electrode layer; and
a second electrode layer formed on the ferroelectric layer.

8. The negative capacitance FinFET device of claim 7 ,
wherein the first electrode layer and the second electrode layer include at least one of lantanium strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru).

9. The negative capacitance FinFET device of claim 7 ,
wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 .

10. A manufacturing method of a negative capacitance FinFET device, comprising:
forming, on a substrate, a FinFET device including a gate stack, a drain electrode and a source electrode;
forming a ferroelectric negative capacitor having a negative capacitance; and
connecting the ferroelectric negative capacitor to the gate stack of the FinFET device,
wherein the FinFET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode, and
the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.

11. The manufacturing method of claim 10 ,
wherein the extension length is set to be in a range from 80 nm to 150 nm.

12. The manufacturing method of claim 10 ,
wherein the extension length is set to be in a range from 120 nm to 150 nm.

13. The manufacturing method of claim 12 ,
wherein the size of the hysteresis window in the negative capacitance FinFET device is from 0.4 V to 0.5 V.

14. The manufacturing method of claim 10 ,
wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 60 mV/decade at room temperature.

15. The manufacturing method of claim 10 ,
wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 20 mV/decade at room temperature.

16. The manufacturing method of claim 10 ,
wherein the forming of a ferroelectric negative capacitor includes:
forming a substrate;
forming a first electrode layer on the substrate;
forming a ferroelectric layer on the first electrode layer; and
forming a second electrode layer on the ferroelectric layer.

17. The manufacturing method of claim 16 ,
wherein the first electrode layer and the second electrode layer include at least one of lantanium strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru).

18. The manufacturing method of claim 16 ,
wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 .

Assignees

• Univ Seoul Ind Coop Found

Inventors

• Shin Chang Hwan
• Ko Eun Ah

Classifications

• H10D84/813 Primary

  Combinations of field-effect devices and capacitor only · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L28/55

  Electricity · mapped topic

• H01L27/0733 Primary

  Electricity · mapped topic