Semiconductor device and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9831179-B2
Application number	US-201615191558-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Aug 25, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of line patterns spaced apart from one another formed on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction;
a first line pattern of the plurality of line patterns, the first line pattern including a wider portion having a second width greater than the first width in a second direction perpendicular to the first direction;
a second line pattern of the plurality of line patterns and located adjacent to the first line pattern, the second line pattern being spaced apart from the wider portion of the first line pattern and conformally formed about the wider portion of the first line pattern; and
a third line pattern selected from the plurality of line patterns and located adjacent to the second line pattern, the third line pattern including an end portion,
wherein the plurality of line patterns comprises a plurality of second line patterns and a plurality of third line patterns,
the wider portion of the first line pattern protrude from both sidewalls of the first line pattern in the second direction, and
two second line patterns are respectively located on both sides of the wider portion, and the two second line patterns are spaced apart from the wider portion of the first line pattern and conformally formed about the wider portion of the first line pattern.

2. The device of claim 1 , wherein
two third line patterns are located adjacent to the respective second line patterns, and include respective end portions, and, with respect to a line extending in the second direction that intersects the third line pattern at the respective end portions of the third line patterns, the distances between respective first line patterns and respective second line patterns are substantially the same as the distances between the respective second line patterns and the respective third line patterns.

3. The device of claim 2 , wherein the two second line patterns are in a mirror-image relationship to each other with respect to the wider portion of the first line pattern.

4. The device of claim 2 , wherein the end portions of the two third line patterns face the conformally formed portions of the two second line patterns in the first direction respectively.

5. The device of claim 2 , wherein the end portions of the third line patterns are spaced apart from the conformally formed portions of the second line patterns by a substantially same distance as the first width.

6. The device of claim 1 , wherein a length of the third line pattern is less than a length of the first line pattern and the second line pattern in the first direction.

7. The device of claim 1 , wherein the plurality of line patterns further comprise a dummy line pattern located opposite the end portion of the third line pattern across the conformally formed portion of the second line pattern in the first direction,
wherein the dummy line pattern has a substantially same width as the first width and is parallel to the first direction.

8. The device of claim 7 , wherein a length of the dummy line pattern is less than a length of the first line pattern and the second line pattern in the first direction.

9. The device of claim 1 , wherein the wider portion of the first line pattern has a third width in the first direction, the conformally formed portion of the second line pattern has a fourth width in the first direction, and the fourth width is greater than the third width.

10. The device of claim 1 , wherein a fourth line pattern is located adjacent to the third line pattern, and a minimum space between the fourth line pattern and the conformally formed portion of the second line pattern is substantially equal to the first width.

11. The device of claim 1 , wherein a fourth line pattern is located adjacent to the third line pattern, and a minimum space between the fourth line pattern and the conformally formed portion of the second line pattern is greater than the first width.

12. The device of claim 1 , wherein the plurality of line patterns comprise a plurality of bit lines included in a memory device of the semiconductor device.

13. A semiconductor device comprising:
a plurality of line patterns spaced apart from one another formed on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction;
a first line pattern of the plurality of line patterns, the first line pattern including a wider portion having a second width greater than the first width in a second direction perpendicular to the first direction;
a second line pattern of the plurality of line patterns and located adjacent to the first line pattern, the second line pattern being spaced apart from the wider portion of the first line pattern and conformally formed about the wider portion of the first line pattern; and
a third line pattern selected from the plurality of line patterns and located adjacent to the second line pattern, the third line pattern including an end portion,
wherein the second line pattern is formed between the first line pattern and the third line pattern, and, with respect to a line extending in the second direction that intersects the third line pattern at the end portion of the third line pattern, the distance between the first line pattern and the second line pattern is substantially the same as the distance between the second line pattern and the third line pattern,
wherein the wider portion protrudes from one sidewall of the first line pattern, the second line pattern is located in a position facing the wider portion, and the end portion of the third line pattern is located near the conformally formed portion of the second line pattern,
wherein the end portion of the third line pattern is spaced apart from the conformally formed portion of the second line pattern by a substantially same distance as the first width in the first direction.

14. The device of claim 13 , wherein the end portion of the third line pattern faces the conformally formed portion of the second line pattern in the first direction.

15. The device of claim 13 , wherein the wider portion is a contact pad and the device further comprises a conductive via in contact with the contact pad.

16. A semiconductor device comprising:
a plurality of line patterns formed on a substrate having a first width and extending in a first direction parallel to one another, the plurality of line patterns spaced apart from one another in a second direction perpendicular to the first direction;
a first line pattern of the plurality of line patterns, the first line pattern including a first wider portion having a second width taken in the second direction greater than the first width taken in the second direction;
a second line pattern of the plurality of line patterns located adjacent to the first line pattern, the second line pattern comprising a second wider portion having a third width greater than the first width in the second direction and a first conformal portion conformally formed about the first wider portion and spaced apart from the first wider portion; and
a third line pattern of the plurality of line patterns and located adjacent to the second line pattern, the third line pattern comprising a third wider portion having a fourth width in the second direction greater than the first width, a second conformal portion conformally formed about the second wider portion and spaced apart from the second wider portion, and an end portion located near the first conformal portion,
wherein the second line pa

Assignees

• Kim Kyoung-Hoon
• Yang Woo-Sung
• Hwang Jee-Hoon
• Samsung Electronics Co Ltd

Inventors

• Kim Kyoung-Hoon
• Yang Woo-Sung
• Hwang Jee-Hoon

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title